SLLSFF6 September   2021 TLIN1024A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings - IEC
    4. 7.4 Thermal Information
    5. 7.5 Recommended Operating Conditions
    6. 7.6 Electrical Characteristics
    7. 7.7 Duty Cycle Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN (Local Interconnect Network) Bus
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD (Transmit Input and Output)
      3. 9.3.3  RXD (Receive Output)
      4. 9.3.4  VSUP1/2 (Supply Voltage)
      5. 9.3.5  GND1/2 (Ground)
      6. 9.3.6  EN (Enable Input)
      7. 9.3.7  Protection Features
      8. 9.3.8  TXD Dominant Time Out (DTO)
      9. 9.3.9  Bus Stuck Dominant System Fault: False Wake-Up Lockout
      10. 9.3.10 Thermal Shutdown
      11. 9.3.11 Under Voltage on VSUP
      12. 9.3.12 Unpowered Device and LIN Bus
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Wake-Up Request (RXD)
        2. 9.4.4.2 Mode Transitions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Detailed Design Procedures
        2. 10.2.1.2 Normal Mode Application Note
        3. 10.2.1.3 Standby Mode Application Note
        4. 10.2.1.4 TXD Dominant State Timeout Application Note
      2. 10.2.2 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Duty Cycle Characteristics

parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
D112V Duty Cycle 1 (ISO/DIS 17987 Param 27)(3) THREC(MAX) = 0.744 x VSUP THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.396
D112V Duty Cycle 1 (3) THREC(MAX) = 0.625 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.396
D1 Duty Cycle 1 (1) (2) THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 18 V, tBIT = 52 μs
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.396
D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) (3) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.581
D212V Duty Cycle 2 (3) THREC(MIN) = 0.546 x VSUP, THDOM(MIN) = 0.4 x VSUP, VSUP = 4 V to 7 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.581
D2 Duty Cycle 2 (1) (2) THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 7 V to 18 V, tBIT = 52 μs
D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.581
D312V Duty Cycle 3 (ISO/DIS 17987 Param 29) (3) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.417
D312V Duty Cycle 3 (3) THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.417
D3 Duty Cycle 3 (1) (2) THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 μs
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.417
D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) (3) THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.59
D412V Duty Cycle 4 (3) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.59
D4 Duty Cycle 4 (1) (2) THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 μs
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.59
D1LB Duty cycle 1 at low battery (1) (2) THREC(MAX) = 0.665 x VSUP,
THDOM(MAX) = 0.499 x VSUP,
VSUP = 5.5 V to 7 V, tBIT = 52 μs		 0.396
D2LB Duty cycle 2 at low battery (1) (2) THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 52 μs		 0.581
D3LB Duty cycle 3 at low battery (1) (2) THREC(MAX) = 0.665 x VSUP,
THDOM(MAX) = 0.499 x VSUP,
VSUP = 5.5 V to 7 V, tBIT = 96 μs		 0.396
D4LB Duty cycle 4 at low battery (1) (2) THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 96 μs		 0.581
Tr-d max Transmitter propagation delay timings for the duty cycle (1) (2)
Recessive to dominant		 THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 52 μs
tREC(MAX)_D1 - tDOM(MIN)_D1 		10.8 µs
Td-r max Transmitter propagation delay timings for the duty cycle (1) (2)
Dominant to recessive		 THREC(MAX) = 0.422 x VSUP,
THDOM(MAX) = 0.284 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 52 μs
tDOM(MAX)_D2 - tREC(MIN)_D2 		8.4 µs
Tr-d max Transmitter propagation delay timings for the duty cycle (1) (2)
Recessive to dominant		 THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 96 μs
tREC(MAX)_D3 - tDOM(MIN)_D3 		15.9 µs
Td-r max Transmitter propagation delay timings for the duty cycle (1) (2)
Dominant to recessive		 THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 96 μs
tDOM(MAX)_D4 - tREC(MIN)_D4 		17.28 µs
Tr-d max_low Low battery transmitter propagation delay timings for the duty cycle (1) (2)
Recessive to dominant		 THREC(MAX) = 0.665 x VSUP,
THDOM(MAX) = 0.499 x VSUP
5.5 V ≤ VSUP ≤ 7 V, tBIT = 52 μs
tREC(MAX)_low - tDOM(MIN)_low 		10.8 µs
Td-r max_low Low battery transmitter propagation delay timings for the duty cycle (1) (2)
Dominant to recessive		 THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
6.1 V ≤ VSUP ≤ 7 V, tBIT = 52 μs
tDOM(MAX)_low - tREC(MIN)_low 		8.4 µs
(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ
(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.