SLOS270F March   2001  – August 2016 TLV2370 , TLV2371 , TLV2372 , TLV2373 , TLV2374 , TLV2375


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information: TLV2370
    4. 7.4  Thermal Information: TLV2371
    5. 7.5  Thermal Information: TLV2372
    6. 7.6  Thermal Information: TLV2373
    7. 7.7  Thermal Information: TLV2374
    8. 7.8  Thermal Information: TLV2375
    9. 7.9  Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail-to-Rail Input Operation
      2. 8.3.2 Driving a Capacitive Load
      3. 8.3.3 Offset Voltage
      4. 8.3.4 General Configurations
      5. 8.3.5 Shutdown Function
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

To achieve the levels of high performance of the TLV237x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following.

  • Ground planes—TI highly recommends using a ground plane on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance.
  • Proper power supply decoupling—Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-μF capacitor must be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
  • Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation.
  • Short trace runs and compact part placements—Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout must be made as compact as possible, thereby minimizing the length of all trace runs. Pay particular attention to the inverting input of the amplifier. Its length must be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier.
  • Surface-mount passive components—Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, TI recommends that the lead lengths be kept as short as possible.

11.2 Layout Example

TLV2370 TLV2371 TLV2372 TLV2373 TLV2374 TLV2375 PCB_SCH_SLOS270.gif Figure 40. Schematic Representation
TLV2370 TLV2371 TLV2372 TLV2373 TLV2374 TLV2375 ground_plane_other_layers_sbos073.gif Figure 41. Operational Amplifier Board Layout for Noninverting Configuration

11.3 Power Dissipation Considerations

For a given θJA, the maximum power dissipation is shown in Figure 42 and is calculated by Equation 4:

Equation 4. TLV2370 TLV2371 TLV2372 TLV2373 TLV2374 TLV2375 equation_01_slos270.gif


  • PD = Maximum power dissipation of TLV237x IC (watts)
  • TMAX = Absolute maximum junction temperature (150°C)
  • TA = Free-ambient air temperature (°C)
  • θJA = θJC (Thermal coefficient from junction to case) + θCA (Thermal coefficient from case to ambient air (°C/W))
TLV2370 TLV2371 TLV2372 TLV2373 TLV2374 TLV2375 maximum_power_dissipation_vs_free_air_temp_slos270.gif
Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 42. Maximum Power Dissipation vs Free-Air Temperature