SBOS754A March   2016  – March 2016 TLV2314 , TLV314 , TLV4314

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TLV314
    5. 7.5 Thermal Information: TLV2314
    6. 7.6 Thermal Information: TLV4314
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Input
      3. 8.3.3 Rail-to-Rail Output
      4. 8.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5 Capacitive Load and Stability
      6. 8.3.6 EMI Susceptibility and Input Filtering
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
    1. 10.1 Input and ESD Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage 7 V
Signal input pins Voltage(2) (V–) – 0.5 (V+) + 0.5 V
Current(2) –10 10 mA
Output short-circuit(3) Continuous mA
Temperature Specified, TA –40 125 °C
Junction, TJ 150
Storage, Tstg –65 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage Single supply 1.8 5.5 V
Dual supply ±0.9 ±2.75
Specified temperature range –40 125 °C

7.4 Thermal Information: TLV314

THERMAL METRIC(1) TLV314 UNIT
DBV (SOT-23) DCK (SC70)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 228.5 281.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 99.1 91.6 °C/W
RθJB Junction-to-board thermal resistance 54.6 59.6 °C/W
ψJT Junction-to-top characterization parameter 7.7 1.5 °C/W
ψJB Junction-to-board characterization parameter 53.8 58.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Thermal Information: TLV2314

THERMAL METRIC(1) TLV2314 UNIT
D (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 138.4 191.2 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 89.5 61.9 °C/W
RθJB Junction-to-board thermal resistance 78.6 111.9 °C/W
ψJT Junction-to-top characterization parameter 29.9 5.1 °C/W
ψJB Junction-to-board characterization parameter 78.1 110.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.6 Thermal Information: TLV4314

THERMAL METRIC(1) TLV4314 UNIT
D (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 93.2 121 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 51.8 49.4 °C/W
RθJB Junction-to-board thermal resistance 49.4 62.8 °C/W
ψJT Junction-to-top characterization parameter 13.5 5.9 °C/W
ψJB Junction-to-board characterization parameter 42.2 62.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.7 Electrical Characteristics

VS = 1.8 V to 5.5 V; at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = (VS+) – 1.3 V, TA = 25°C ±0.75 ±3 mV
dVOS/dT VOS vs temperature TA = –40°C to +125°C 2 μV/°C
PSRR Power-supply rejection ratio VCM = (VS+) – 1.3 V, TA = 25°C ±30 ±135 µV/V
Channel separation, dc At dc, TA = 25°C 100 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range TA = 25°C (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V,
TA = 25°C		 72 96 dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V(2), TA = 25°C 75
INPUT BIAS CURRENT
IB Input bias current TA = 25°C ±1.0 pA
IOS Input offset current TA = 25°C ±1.0 pA
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz, TA = 25°C 5 μVPP
en Input voltage noise density f = 10 kHz, TA = 25°C 15 nV/√Hz
f = 1 kHz, TA = 25°C 16
in Input current noise density f = 1 kHz, TA = 25°C 6 fA/√Hz
INPUT CAPACITANCE
CIN Input capacitance Differential VS = 5 V, TA = 25°C 1 pF
Common-mode VS = 5 V, TA = 25°C 5
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8 V to 5.5 V, 0.2 V < VO < (V+) – 0.2 V,
RL = 10 kΩ, TA = 25°C		 85 115 dB
VS = 1.8 V to 5.5 V, 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ(2), TA = 25°C		 85 100
Phase margin VS = 5 V, G = 1, RL = 10 kΩ, TA = 25°C 65 °
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 1.8 V, RL = 10 kΩ, CL = 10 pF, TA = 25°C 2.7 MHz
VS = 5 V, RL = 10 kΩ, CL = 10 pF, TA = 25°C 3
SR Slew rate(3) VS = 5 V, G = 1, TA = 25°C 1.5 V/μs
tS Settling time To 0.1%, VS = 5 V, 2-V step , G = 1, TA = 25°C 3 μs
Overload recovery time VS = 5 V, VIN  × gain > VS, TA = 25°C 8 μs
THD+N Total harmonic distortion + noise(4) VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz,
RL = 10 kΩ, TA = 25°C		 0.005%
OUTPUT
VO Voltage output swing from supply rails VS = 1.8 V to 5.5 V, RL = 10 kΩ, TA = 25°C 5 25 mV
VS = 1.8 V to 5.5 V, RL = 2 kΩ, TA = 25°C 22 45
ISC Short-circuit current VS = 5 V, TA = 25°C ±20 mA
RO Open-loop output impedance VS = 5.5 V, f = 100 Hz, TA = 25°C 570 Ω
POWER SUPPLY
VS Specified voltage range 1.8 5.5 V
IQ Quiescent current per amplifier, over temperature VS = 5 V, IO = 0 mA, TA = –40°C to +125°C 150 250 µA
TEMPERATURE
Specified range –40 125 °C
Tstg Storage range –65 150 °C
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over-temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.
(3) Signifies the slower value of the positive or negative slew rate.
(4) Third-order filter; bandwidth = 80 kHz at –3 dB.

7.8 Typical Characteristics

Table 1. Table of Graphs

TITLE FIGURE
Open-Loop Gain and Phase vs Frequency Figure 1
Quiescent Current vs Supply Voltage Figure 2
Offset Voltage Production Distribution Figure 3
Offset Voltage vs Common-Mode Voltage (Maximum Supply) Figure 4
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V) Figure 5
Input Bias and Offset Current vs Temperature Figure 6
Output Voltage Swing vs Output Current (over Temperature) Figure 7
Small-Signal Overshoot vs Load Capacitance Figure 8
Small-Signal Step Response, Noninverting (1.8 V) Figure 9
Large-Signal Step Response, Noninverting (1.8 V) Figure 10
No Phase Reversal Figure 11
Channel Separation vs Frequency (Dual) Figure 12
EMIRR Figure 13

7.9 Typical Characteristics

at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
TLV314 TLV2314 TLV4314 tc_open_loop_gain_phase_fqcy_sbos754.gif
RL = 10 kΩ and 10 pF, VS = ±2.5 V
Figure 1. Open-Loop Gain and Phase vs Frequency
TLV314 TLV2314 TLV4314 tc_histo_voffset_sbos754.gif
Figure 3. Offset Voltage Production Distribution
TLV314 TLV2314 TLV4314 tc_vin_spec_density_fqcy_bos563.gif
Figure 5. Input Voltage Noise Spectral Density vs
Frequency
TLV314 TLV2314 TLV4314 tc_vout_swing_iout_sbos754.gif
VS = ±2.75 V
Figure 7. Output Voltage Swing vs Output Current
(Over Temperature)
TLV314 TLV2314 TLV4314 tc_sm_sig_step_09V_sbos754.gif
VS = ±0.9 V, gain = 1 V/V, RF = 10 kΩ
Figure 9. Small-Signal Pulse Response (Noninverting)
TLV314 TLV2314 TLV4314 tc_anti_phase_reversal_bos563.gif
Figure 11. No Phase Reversal
TLV314 TLV2314 TLV4314 tc_emirr_2314_sbos754.gif
PRF = –10 dBm, VS = ±2.5 V, VCM = 0 V
Figure 13. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR IN+) vs Frequency
TLV314 TLV2314 TLV4314 tc_iq_vsupply_sbos754.gif
Figure 2. Quiescent Current vs Supply
TLV314 TLV2314 TLV4314 tc_vos_vcm_sbos754.gif
Typical units, VS = ±2.75 V
Figure 4. Offset Voltage vs Common-Mode Voltage
TLV314 TLV2314 TLV4314 tc_input_bias_temp_sbos754.gif
Figure 6. Input Bias and Offset Current vs Temperature
TLV314 TLV2314 TLV4314 tc_sm_sig_ovrsht_cap_load_sbos754.gif
VS = ±2.75 V, gain = 1 V/V, RL = 10 kΩ
Figure 8. Small-Signal Overshoot vs Load Capacitance
TLV314 TLV2314 TLV4314 tc_lg_sig_step_09V_sbos754.gif
VS = ±0.9 V, gain = 1 V/V, RL = 10 kΩ
Figure 10. Large-Signal Pulse Response (Noninverting)
TLV314 TLV2314 TLV4314 tc_chan_separat_fqcy_sbos754.gif
VS = ±2.75 V
Figure 12. Channel Separation vs Frequency (TLV2314)