SLAS549D September   2008  – November 2014 TLV320AIC3254

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics, ADC
    6. 8.6  Electrical Characteristics, Bypass Outputs
    7. 8.7  Electrical Characteristics, Microphone Interface
    8. 8.8  Electrical Characteristics, Audio DAC Outputs
    9. 8.9  Electrical Characteristics, LDO
    10. 8.10 Electrical Characteristics, Misc.
    11. 8.11 Electrical Characteristics, Logic Levels
    12. 8.12 I2S LJF and RJF Timing in Master Mode (see )
    13. 8.13 I2S LJF and RJF Timing in Slave Mode (see )
    14. 8.14 DSP Timing in Master Mode (see )
    15. 8.15 DSP Timing in Slave Mode (see )
    16. 8.16 Digital Microphone PDM Timing (see )
    17. 8.17 I2C Interface Timing
    18. 8.18 SPI Interface Timing (See )
    19. 8.19 Typical Characteristics
    20. 8.20 Typical Characteristics, FFT
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Connections
        1. 10.3.1.1 Digital Pins
          1. 10.3.1.1.1 Multifunction Pins
        2. 10.3.1.2 Analog Pins
      2. 10.3.2 Analog Audio IO
        1. 10.3.2.1 Analog Low Power Bypass
        2. 10.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 10.3.2.3 Headphone Outputs
        4. 10.3.2.4 Line Outputs
      3. 10.3.3 ADC
        1. 10.3.3.1 ADC Processing
          1. 10.3.3.1.1 ADC Processing Blocks
      4. 10.3.4 DAC
        1. 10.3.4.1 DAC Processing Blocks
      5. 10.3.5 PowerTune
      6. 10.3.6 Digital Audio IO Interface
      7. 10.3.7 Clock Generation and PLL
      8. 10.3.8 Control Interfaces
        1. 10.3.8.1 I2C Control
        2. 10.3.8.2 SPI Control
    4. 10.4 Device Functional Modes
    5. 10.5 Software
    6. 10.6 Register Map
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Reference Filtering Capacitor
        2. 11.2.1.2 MICBIAS
      2. 11.2.2 Detailed Design Procedures
        1. 11.2.2.1 Analog Input Connection
        2. 11.2.2.2 Analog Output Connection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

11.1 Application Information

The TLV320AIC3254 is a highly integrated stereo audio codec with integrated miniDSP and flexible digital audio interface options. It enables many different types of audio platforms having a need for stereo audio record and playback and needing to interface with other devices in the system over a digital audio interface.

11.2 Typical Application

Figure 21 shows a typical circuit configuration for a system using theTLV320AIC3254.

typckt_los602.gifFigure 21. Typical Circuit Configuration

11.2.1 Design Requirements

11.2.1.1 Reference Filtering Capacitor

The TLV320AIC3254 has a built-in bandgap used to generate reference voltages and currents for the device. To achieve high SNR, the reference voltage on REF should be filtered using a 10-μF capacitor from REF terminal to ground.

11.2.1.2 MICBIAS

The TLV320AIC3254 has a built-in bias voltage output for biasing of microphones. No intentional capacitors should be connected directly to the MICBIAS output for filtering.

11.2.2 Detailed Design Procedures

11.2.2.1 Analog Input Connection

The analog inputs to TLV320AIC3254 should be ac-coupled to the device terminals to allow decoupling of signal source's common mode voltage with that of TLV320AIC3254's common mode voltage. The input coupling capacitor in combination with the selected input impedance of TLV320AIC3254 forms a high-pass filter.

Equation 1. Fc = 1/(2 x π x ReqCc)
Equation 2. Cc = 1/(2 x π x ReqFc)

For high fidelity audio recording application it is desirable to keep the cutoff frequency of the high pass filter as low as possible. For single-ended input mode, the equivalent input resistance Req can be calculated as

Equation 3. Req = Rin x (1 + 2g)/(1+g)

where g is the analog PGA gain calculated in linear terms.

Equation 4. g = 10000 x 2floor(G/6)/Rin

where G is the analog PGA gain programmed in P1_R59-R60 (in dB) and Rin is the value of the resistor programmed in P1_R52-R57 and assumes Rin = Rcm (as defined in P1_R52-R57).

For differential input mode, Req of the half circuit can be calculated as:

Equation 5. Req = Rin

where Rin is the value of the resistor programmed in P1_R52-R57, assuming symmetrical inputs.

aic3268_schem_app_ana_in_1r.gifFigure 22. Analog Input Connection With Pull-down Resistor

When the analog signal is connected to the system through a connector such as audio jack, it is recommended to put a pull-down resistor on the signal as shown in Figure 22. The pulldown resistor helps keep the signal grounded and helps improve noise immunity when no source is connected to the connector. The pulldown resistor value should be chosen large enough to avoid loading of signal source.

Each analog input of the TLV320AIC3254 is capable of handling signal amplitude of 0.5 Vrms. If the input signal source can drive signals higher than the maximum value, an external resistor divider network as shown in Figure 23 should be used to attenuate the signal to less than 0.5Vrms before connecting the signal to the device. The resistor values of the network should be chosen to provide desired attenuation as well as Equation 6.

Equation 6. R1|| R2<< Req
aic3268_schem_app_ana_in_2r.gifFigure 23. Analog Input Connection With Resistor Divider Network

Whenever any of the analog input terminals IN1_L, IN2_L, IN3_L, IN1_R, IN2_R or IN3_R are not used in an application, it is recommended to short the unused input terminals together (if convenient) and connect them to ground using a small capacitor (example 0.1 µF).

11.2.2.2 Analog Output Connection

The line outputs of the TLV320AIC3254 drive a signal biased around the device common mode voltage. To avoid loading the common mode with the load, it is recommended to connect the single-ended load through an ac-coupling capacitor. The ac-coupling capacitor in combination with the load impedance forms a high pass filter.

Equation 7. Fc = 1/(2 x π x RLCc)
Equation 8. Cc = 1/(2 x π x RLFc)

For high fidelity playback, the cutoff frequency of the resultant high-pass filter should be kept low. For example with RL of 10 kΩ, using 1-µF coupling capacitor results in a cut-off frequency of 8 Hz.

For differential lineout configurations, the load should be directly connected between the differential outputs, with no coupling capacitor.

Whenever any of the analog output terminals LOL, LOR, HPL or HPR are not used in an application, they should be left open or not connected.

11.2.3 Application Curves

Figure 24 shows the excellent low-distortion performance of the TLV320AIC3254 in a system over the 20-Hz to 20-kHz audio spectrum.

Figure 25 shows the distortion performance of the TLV320AIC3254 in a system over the input amplitude range.

G002_slos602.gif
Differential Lineout Rload = 10 kΩ CM = 0.9 V
Input Amplitude = -3 dBFS
Figure 24. Total Harmonic Distortion + Noise vs
Input Frequency
D001_SLOS602.gif
Differential Lineout Rload = 10 kΩ CM = 0.9 V
Frequency = 997 Hz
Figure 25. Total Harmonic Distortion + Noise vs
Input Amplitude