SLAS538B October   2007  – November 2016 TLV320AIC34

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hardware Reset
      2. 9.3.2  I2C Bus Debug In A Glitched System
      3. 9.3.3  Digital Audio Data Serial Interface
      4. 9.3.4  TDM Data Transfer
      5. 9.3.5  Audio Data Converters
      6. 9.3.6  Audio Clock Generation
      7. 9.3.7  Stereo Audio ADC
        1. 9.3.7.1 Stereo Audio ADC High-pass Filter
      8. 9.3.8  Digital Audio Processing For Record Path
      9. 9.3.9  Automatic Gain Control (AGC)
      10. 9.3.10 Stereo Audio DAC
      11. 9.3.11 Digital Audio Processing For Playback
      12. 9.3.12 Digital Interpolation Filter
      13. 9.3.13 Delta-Sigma Audio DAC
      14. 9.3.14 Audio DAC Digital Volume Control
      15. 9.3.15 Increasing DAC Dynamic Range
      16. 9.3.16 Analog Output Common-Mode Adjustment
      17. 9.3.17 Audio DAC Power Control
      18. 9.3.18 Audio Analog Inputs
      19. 9.3.19 Analog Input Bypass Path Functionality
      20. 9.3.20 ADC PGA Signal Bypass Path Functionality
      21. 9.3.21 Input Impedance and VCM Control
      22. 9.3.22 Passive Analog Bypass During Power Down
      23. 9.3.23 MICBIAS_x Generation
      24. 9.3.24 Digital Microphone Connectivity
      25. 9.3.25 Analog Fully Differential Line Output Drivers
      26. 9.3.26 Analog High-Power Output Drivers
      27. 9.3.27 Short-Circuit Output Protection
      28. 9.3.28 Jack or Headset Detection
      29. 9.3.29 Output Stage Volume Controls
    4. 9.4 Device Functional Modes
      1. 9.4.1 I2C Control Mode
      2. 9.4.2 Right-Justified Mode
      3. 9.4.3 Left-Justified Mode
      4. 9.4.4 I2S Mode
      5. 9.4.5 DSP Mode
    5. 9.5 Programming
      1. 9.5.1 Digital Control Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZAS|87
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

The record path of the TLV320AIC34 contains integrated microphone bias, digitally controlled four-channel microphone preamplifier, and automatic gain control (AGC), with mix or mux capability among the multiple analog inputs. Programmable filters are available during record which can remove audible noise that can occur during optical zooming in digital cameras. The playback path includes mix or mux capability from the four-channel DAC and selected inputs, through programmable volume controls, to the various outputs.

The TLV320AIC34 contains eight high-power output drivers as well as six line-level output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to eight channels of single-ended 16-Ω headphones using ac-coupling capacitors, or four channels in a capless output configuration. In addition, for codec A, pairs of drivers can be used to drive mono or stereo 8-Ω speakers directly in a BTL configuration at 500 mW per channel.

The four-channel audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in each path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48-kHz rates. The four-channel audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers providing up to 59.5-dB analog gain for low-level microphone inputs. The TLV320AIC34 provides an extremely high range of programmability for both attack (8 to 1,408 ms) and for decay (0.05 to 22.4 seconds). This extended AGC range allows the AGC to be tuned for many types of applications.

For battery saving applications where neither analog nor digital signal processing is required, the device can be put in a special analog signal pass-through mode. This mode significantly reduces power consumption, as most of the device is powered down during this pass through operation.

The serial control bus supports normal-speed and fast I2C protocols, whereas the dual serial audio data busses are programmable for I2S, left- or right-justified, DSP, PCM, or TDM mode. Two highly programmable PLLs are included for flexible clock generation and support for all standard audio rates from a wide range of available MCLK_x frequencies, varying from 512 kHz to 50 MHz, with special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.

The TLV320AIC34 operates from an analog supply of 2.7 V to 3.6 V, a digital core supply of 1.65 V to 1.95 V, and a digital I/O supply of 1.1 V to 3.6 V. The device is available in a 6-mm × 6-mm, 87-ball NFBGA package.