SLAS671C Data sheet

SLAS671C February 2010 – January 2017 TLV320DAC3100

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RHB|32
- MPQF130D

Thermal pad, mechanical data (Package|Pins)

RHB|32
- QFND029X

Orderable Information

6 Detailed Description

6.1 Overview

The TLV320DAC3100 device is a highly integrated stereo-audio DAC for portable computing, communication, and entertainment applications. A register-based architecture eases integration with microprocessor-based systems through standard serial-interface buses. This device supports the two-wire I²C bus interface which provides full register access. All peripheral functions are controlled through these registers and the onboard state machines.

The TLV320DAC3100 device consists of the following blocks:

Stereo Audio DAC
Dynamic range compressor (DRC)
Digital sine-wave generator for clicks and beeps
Stereo headphone and lineout amplifier
Pin-controlled or register-controlled volume level
Power-down de-pop and power-up soft start
Analog inputs
I²C control interface
Power-down control block

Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I²C interface is used to write to the control registers to configure the device.

The I²C address assigned to the TLV320DAC3100 device is 001 1000. This device always operates in an I²C slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device auto-increments to support sequential addressing and can be used with the I²C fast mode. When the device is reset, all appropriate registers are updated by the host processor to configure the device as needed by the user.

6.2 Functional Block Diagram

6.3 Feature Description

6.3.1 Power-Supply Sequence

The TLV320DAC3100 requires multiple power supply rails for operation. All the power rails must be powered up for the device to operate at the fullest potention. The following is the recommended power-up sequencing for proper operation:

Power up SPKVDD and SPRVDD
Power up IOVDD
Power up DVDD shortly after IOVDD
Power up AVDD and HPVDD

Although not necessary, if the system requires, during shutdown, remove the power supplies in the reverse order of the above sequence.

6.3.2 Reset

The TLV320DAC3100 internal logic must be initialized to a known condition for proper device function. To initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up. TI recommends that while the DVDD supply powers up, the RESET pin is pulled low.

The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the device.

6.3.3 Device Start-Up Lockout Times

After the TLV320DAC3100 is initialized through hardware reset at power up or software reset, the internal memories are initialized to default values. This initialization takes place within 1 ms after pulling the RESET signal high. During this initialization phase, no register-read or register-write operation should be performed on DAC coefficient buffers. Also, no block within the codec should be powered up during the initialization phase.

6.3.4 PLL Start-Up

Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up command of the PLL and before the clocks are available to the codec. This delay is to ensure stable operation of the PLL and clock-divider logic.

6.3.5 Power-Stage Reset

The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has occurred. Using this reset re-enables the output stage without resetting all of the registers in the device. Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is performed by setting page 1/ register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for HPR. The speaker power-stage reset is performed by setting page 1 / register 32, bit D7 for SPKP and SPKM.

6.3.6 Software Power Down

By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit block can be controlled by writing to the appropriate control register. This approach allows the lowest power-supply current for the functionality required. However, when a block is powered down, all of the register settings are maintained as long as power is still being applied to the device.

6.3.7 Audio Analog I/O

The TLV320DAC3100 has a stereo audio DAC. The device supports a wide range of analog interfaces to support different headsets and analog outputs. The TLV320DAC3100 has features to interface output drivers (8-Ω, 16-Ω, 32-Ω). A special circuit has also been included in the TLV320DAC3100 to insert a short key-click sound into the stereo audio output. The key-click sound is used to provide feedback to the user when a particular button is pressed or item is selected. The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency, duration, and amplitude (see Section 6.3.10.7).

6.3.8 Digital Processing Low-Power Modes

The TLV320DAC3100 device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application. The choice of processing blocks, PRB_P1 to PRB_P25 for stereo playback, also influences the power consumption. In fact, the numerous processing blocks have been implemented to offer a choice among configurations having a different balance of power optimization and signal-processing capabilities.

6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 24.28 mW

Table 6-1 PRB_P7 Alternative Processing Blocks, 24.28 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P1	A	1.34
PRB_P2	A	2.86
PRB_P3	A	2.11
PRB_P8	B	1.18
PRB_P9	B	0.53
PRB_P10	B	1.89
PRB_P11	B	0.87
PRB_P23	A	1.48
PRB_P24	A	2.89
PRB_P25	A	3.23

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 24.5 mW

Table 6-2 PRB_P7 Alternative Processing Blocks, 24.5 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P1	A	1.17
PRB_P2	A	2.62
PRB_P3	A	2
PRB_P8	B	0.99
PRB_P9	B	0.5
PRB_P10	B	1.46
PRB_P11	B	0.66
PRB_P23	A	1.43
PRB_P24	A	2.69
PRB_P25	A	2.92

6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.4 mW

Table 6-3 PRB_P12 Alternative Processing Blocks, 15.4 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P4	A	0.57
PRB_P5	A	1.48
PRB_P6	A	1.08
PRB_P13	B	0.56
PRB_P14	B	0.27
PRB_P15	B	0.89
PRB_P16	B	0.31

DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.54 mW

Table 6-4 PRB_P12 Alternative Processing Blocks, 15.54 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P4	A	0.37
PRB_P5	A	1.23
PRB_P6	A	1.15
PRB_P13	B	0.43
PRB_P14	B	0.13
PRB_P15	B	0.85
PRB_P16	B	0.21

6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.44 mW

Table 6-5 PRB_P7 Alternative Processing Blocks, 22.44 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P1	A	0.02
PRB_P2	A	0.31
PRB_P3	A	0.23
PRB_P8	B	0.28
PRB_P9	B	–0.03
PRB_P10	B	0.14
PRB_P11	B	0.05
PRB_P23	A	0.29
PRB_P24	A	0.26
PRB_P25	A	0.47

DOSR = 384, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.83 mW

Table 6-6 PRB_P7 Alternative Processing Blocks, 22.83 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P1	A	0.27
PRB_P2	A	0.4
PRB_P3	A	0.34
PRB_P8	B	0.2
PRB_P9	B	0.08
PRB_P10	B	0.24
PRB_P11	B	0.12
PRB_P23	A	0.23
PRB_P24	A	0.42
PRB_P25	A	0.46

6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.49 mW

Table 6-7 PRB_P12 Alternative Processing Blocks, 14.49 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P4	A	–0.04
PRB_P5	A	0.2
PRB_P6	A	–0.01
PRB_P13	B	0.1
PRB_P14	B	0.05
PRB_P15	B	–0.03
PRB_P16	B	0.07

DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.42 mW

Table 6-8 PRB_P12 Alternative Processing Blocks, 14.42 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P4	A	0.16
PRB_P5	A	0.3
PRB_P6	A	0.2
PRB_P13	B	0.15
PRB_P14	B	0.07
PRB_P15	B	0.18
PRB_P16	B	0.09

6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C)

Power consumption = 27.05 mW

Table 6-9 PRB_P17 Alternative Processing Blocks, 27.05 mW

PROCESSING BLOCK	FILTER	ESTIMATED POWER CHANGE (mW)
PRB_P18	C	5.28
PRB_P19	C	1.98

6.3.8.6 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V,
HPVDD = 3 V

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 12.85 mW

6.3.9 Analog Signals

The TLV320DAC3100 analog signals consist of:

Microphone bias (MICBIAS)
Analog inputs AIN1 and AIN2
Analog outputs, class-D speaker driver and headphone and lineout driver, providing output capability for the DAC, AIN1, AIN2 or a mix of the three

6.3.9.1 MICBIAS

The TLV320DAC3100 device includes a microphone bias circuit that sources up to 4 mA of current and is programmable to a 2-V, 2.5-V, or AVDD level. The level is controlled by writing to page 1 / register 46, bits D1–D0. Table 6-10 lists this functionality.

Table 6-10 MICBIAS Settings

D1	D0	FUNCTIONALITY
0	0	MICBIAS output is powered down
0	1	MICBIAS output is powered to 2 V
1	0	MICBIAS output is powered to 2.5 V
1	1	MICBIAS output is powered to AVDD

During normal operation, MICBIAS can be set to 2.5 V for better performance. However, based on the model of the selected microphone, optimal performance can be obtained at another setting and therefore the performance at a given setting must be verified.

The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current consumption occurs when MICBIAS is set at AVDD. The highest current consumption occurs when MICBIAS is set at 2 V.

6.3.9.2 Analog Inputs AIN1 and AIN2

AIN1 (pin 13) and AIN2 (pin 14) are inputs to the output mixer along with the DAC output. Page 1 / register 35 provides control signals for determining the signals routed through the output mixer. The output of the output mixer then can be attenuated or gained through the class-D and, or, headphone and lineout drivers.

6.3.10 Audio DAC and Audio Analog Outputs

Each channel of the stereo audio DAC consists of a digital-audio processing block, a digital interpolation filter, a digital delta-sigma modulator, and an analog reconstruction filter. The DAC oversampling ratio (typically DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include stereo headphone, or lineouts, and stereo class-D speaker outputs.

6.3.10.1 DAC

The TLV320DAC3100 stereo-audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the stereo audio-DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, a multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320DAC3100 device allows the system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0 / register 13 and page 0 / register 14. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates.

The TLV320DAC3100 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on required frequency response, group delay, and sampling rate.

DAC power up is controlled by writing to page 0 / register 63, bit D7 for the left channel and bit D6 for the right channel. The left-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7. The right-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D6.

6.3.10.1.1 DAC Processing Blocks

The TLV320DAC3100 device implements signal-processing capabilities and interpolation filtering through processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they use and which interpolation filter is applied.

The choices among these processing blocks allow the system designer to balance power conservation and signal-processing flexibility. Table 6-11 gives an overview of all available processing blocks of the DAC channel and their properties. The resource-class column gives an approximate indication of power consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog power consumption of the drivers (HPVDD) may differ.

The signal processing blocks available are:

First-order IIR
Scalable number of biquad filters
3D effect
Digital sine-wave (beep) generator

The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal-processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients.

Table 6-11 Overview – DAC Predefined Processing Blocks

PROCESSING BLOCK NO.	INTERPOLATION FILTER	CHANNEL	FIRST-ORDER IIR AVAILABLE	NUMBER OF BIQUADS	DRC	3D	BEEP GENERATOR	RESOURCE CLASS
PRB_P1	A	Stereo	No	3	No	No	No	8
PRB_P2	A	Stereo	Yes	6	Yes	No	No	12
PRB_P3	A	Stereo	Yes	6	No	No	No	10
PRB_P4	A	Left	No	3	No	No	No	4
PRB_P5	A	Left	Yes	6	Yes	No	No	6
PRB_P6	A	Left	Yes	6	No	No	No	6
PRB_P7	B	Stereo	Yes	0	No	No	No	6
PRB_P8	B	Stereo	No	4	Yes	No	No	8
PRB_P9	B	Stereo	No	4	No	No	No	8
PRB_P10	B	Stereo	Yes	6	Yes	No	No	10
PRB_P11	B	Stereo	Yes	6	No	No	No	8
PRB_P12	B	Left	Yes	0	No	No	No	3
PRB_P13	B	Left	No	4	Yes	No	No	4
PRB_P14	B	Left	No	4	No	No	No	4
PRB_P15	B	Left	Yes	6	Yes	No	No	6
PRB_P16	B	Left	Yes	6	No	No	No	4
PRB_P17	C	Stereo	Yes	0	No	No	No	3
PRB_P18	C	Stereo	Yes	4	Yes	No	No	6
PRB_P19	C	Stereo	Yes	4	No	No	No	4
PRB_P20	C	Left	Yes	0	No	No	No	2
PRB_P21	C	Left	Yes	4	Yes	No	No	3
PRB_P22	C	Left	Yes	4	No	No	No	2
PRB_P23	A	Stereo	No	2	No	Yes	No	8
PRB_P24	A	Stereo	Yes	5	Yes	Yes	No	12
PRB_P25	A	Stereo	Yes	5	Yes	Yes	Yes	12

6.3.10.1.2 DAC Processing Blocks — Details

6.3.10.1.2.1 Three Biquads, Filter A

Figure 6-1 Signal Chain for PRB_P1 and PRB_P4

6.3.10.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B

TLV320DAC3100 f_3254_b_6bq_iir_drc_interp.gif

Figure 6-2 Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15

6.3.10.1.2.3 Six Biquads, First-Order IIR, Filter A or B

Figure 6-3 Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16

6.3.10.1.2.4 IIR, Filter B or C

Figure 6-4 Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20

6.3.10.1.2.5 Four Biquads, DRC, Filter B

TLV320DAC3100 f_3254_e_4bq_drc_interp.gif

Figure 6-5 Signal Chain for PRB_P8 and PRB_P13

6.3.10.1.2.6 Four Biquads, Filter B

Figure 6-6 Signal Chain for PRB_P9 and PRB_P14

6.3.10.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C

TLV320DAC3100 f_3254_g_4bq_iir_drc_interp.gif

Figure 6-7 Signal Chain for PRB_P18 and PRB_P21

6.3.10.1.2.8 Four Biquads, First-Order IIR, Filter C

Figure 6-8 Signal Chain for PRB_P19 and PRB_P22

6.3.10.1.2.9 Two Biquads, 3D, Filter A

NOTE:

A_L means biquad A of the left channel, and similarly, B_R means biquad B of the right channel.

Figure 6-9 Signal Chain for PRB_P23

6.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A

TLV320DAC3100 f_3254_j_5bq_drc_3d_interp.gif

Figure 6-10 Signal Chain for PRB_P24

6.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A

TLV320DAC3100 f_3254_k_5bq_drc_3d_beep_interp.gif

Figure 6-11 Signal Chain for PRB_P25

6.3.10.1.3 DAC User-Programmable Filters

Based on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks.

The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched in real time.

When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed for either read or write.

However, the TLV320DAC3100 device offers an adaptive filter mode as well. Setting page 8 / register 1, bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients are updated through the host and activated without stopping and restarting the DAC which enables advanced adaptive filtering applications.

In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC is running and the adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At the same time, page 8 / register 1, bit D1 toggles.

The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use.

Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use.

While the device is running, coefficient updates are always made to the buffer not in use by the DAC, regardless of the buffer to which the coefficients have been written.

Table 6-12 Adaptive-Mode Filter-Coefficient Buffer Switching

DAC POWERED UP	PAGE 8 / REGISTER 1, BIT D1	COEFFICIENT BUFFER IN USE	WRITING TO	UPDATES
No	0	None	C1, buffer A	C1, buffer A
No	0	None	C1, buffer B	C1, buffer B
Yes	0	Buffer A	C1, buffer A	C1, buffer B
Yes	0	Buffer A	C1, buffer B	C1, buffer B
Yes	1	Buffer B	C1, buffer A	C1, buffer A
Yes	1	Buffer B	C1, buffer B	C1, buffer A

The user-programmable coefficients for the DAC processing blocks are defined on page 8 and page 9 for buffer A and page 12 and page 13 for buffer B.

The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 6-12.

Figure 6-12 1.15 2s-Complement Coefficient Format

6.3.10.1.3.1 First-Order IIR Section

The IIR is of first order and its transfer function is given by Equation 1.

Equation 1. TLV320DAC3100 Agclpf_LAS550.gif

The frequency response for the first-order IIR section with default coefficients is flat.

Table 6-13 DAC IIR Filter Coefficients

FILTER	COEFFICIENT	LEFT DAC CHANNEL	RIGHT DAC CHANNEL	DEFAULT (RESET) VALUE
First-order IIR	N0	Page 9 / register 2 and page 9 / register 3	Page 9 / register 8 and page 9 / register 9	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 9 / register 4 and page 9 / register 5	Page 9 / register 10 and page 9 / register 11	0x0000
	D1	Page 9 / register 6 and page 9 / register 7	Page 9 / register 12 and page 9 / register 13	0x0000

6.3.10.1.3.2 Biquad Section

The transfer function of each of the biquad filters is given by Equation 2.

Equation 2. TLV320DAC3100 biquad_las550.gif

Table 6-14 DAC Biquad Filter Coefficients

FILTER	COEFFICIENT	LEFT DAC CHANNEL	RIGHT DAC CHANNEL	DEFAULT (RESET) VALUE
Biquad A	N0	Page 8 / register 2 and page 8 / register 3	Page 8 / register 66 and page 8 / register 67	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 4 and page 8 / register 5	Page 8 / register 68 and page 8 / register 69	0x0000
	N2	Page 8 / register 6 and page 8 / register 7	Page 8 / register 70 and page 8 / register 71	0x0000
	D1	Page 8 / register 8 and page 8 / register 9	Page 8 / register 72 and page 8 / register 73	0x0000
	D2	Page 8 / register 10 and page 8 / register 11	Page 8 / register 74 and page 8 / register 75	0x0000
Biquad B	N0	Page 8 / register 12 and page 8 / register 13	Page 8 / register 76 and page 8 / register 77	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 14 and page 8 / register 15	Page 8 / register 78 and page 8 / register 79	0x0000
	N2	Page 8 / register 16 and page 8 / register 17	Page 8 / register 80 and page 8 / register 81	0x0000
	D1	Page 8 / register 18 and page 8 / register 19	Page 8 / register 82 and page 8 / register 83	0x0000
	D2	Page 8 / register 20 and page 8 / register 21	Page 8 / register 84 and page 8 / register 85	0x0000
Biquad C	N0	Page 8 / register 22 and page 8 / register 23	Page 8 / register 86 and page 8 / register 87	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 24 and page 8 / register 25	Page 8 / register 88 and page 8 / register 89	0x0000
	N2	Page 8 / register 26 and page 8 / register 27	Page 8 / register 90 and page 8 / register 91	0x0000
	D1	Page 8 / register 28 and page 8 / register 29	Page 8 / register 92 and page 8 / register 93	0x0000
	D2	Page 8 / register 30 and page 8 / register 31	Page 8 / register 94 and page 8 / register 95	0x0000
Biquad D	N0	Page 8 / register 32 and page 8 / register 33	Page 8 / register 96 and page 8 / register 97	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 34 and page 8 / register 35	Page 8 / register 98 and page 8 / register 99	0x0000
	N2	Page 8 / register 36 and page 8 / register 37	Page 8 / register 100 and page 8 / register 101	0x0000
	D1	Page 8 / register 38 and page 8 / register 39	Page 8 / register 102 and page 8 / register 103	0x0000
	D2	Page 8 / register 40 and page 8 / register 41	Page 8 / register 104 and page 8 / register 105	0x0000
Biquad E	N0	Page 8 / register 42 and page 8 / register 43	Page 8 / register 106 and page 8 / register 107	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 44 and page 8 / register 45	Page 8 / register 108 and page 8 / register 109	0x0000
	N2	Page 8 / register 46 and page 8 / register 47	Page 8 / register 110 and page 8 / register 111	0x0000
	D1	Page 8 / register 48 and page 8 / register 49	Page 8 / register 112 and page 8 / register 113	0x0000
	D2	Page 8 / register 50 and page 8 / register 51	Page 8 / register 114 and page 8 / register 115	0x0000
Biquad F	N0	Page 8 / register 52 and page 8 / register 53	Page 8 / register 116 and page 8 / register 117	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 54 and page 8 / register 55	Page 8 / register 118 and page 8 / register 119	0x0000
	N2	Page 8 / register 56 and page 8 / register 57	Page 8 / register 120 and page 8 / register 121	0x0000
	D1	Page 8 / register 58 and page 8 / register 59	Page 8 / register 122 and page 8 / register 123	0x0000
	D2	Page 8 / register 60 and page 8 / register 61	Page 8 / register 124 and page 8 / register 125	0x0000

6.3.10.1.4 DAC Interpolation Filter Characteristics

6.3.10.1.4.1 Interpolation Filter A

Filter A is designed for an f_S up to 48 ksps with a flat passband of 0 to 20 kHz.

Table 6-15 Specification for DAC Interpolation Filter A

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
Filter-gain pass band	0 … 0.45 f_S	±0.015	dB
Filter-gain stop band	0.55… 7.455 f_S	–65	dB
Filter group delay		21 / f_S	s

Figure 6-13 Frequency Response of DAC Interpolation Filter A

6.3.10.1.4.2 Interpolation Filter B

Filter B is specifically designed for an f_S of up to 96 ksps. Thus, the flat passband region easily covers the required audio band of 0 to 20 kHz.

Table 6-16 Specification for DAC Interpolation Filter B

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
Filter-gain pass band	0 … 0.45 f_S	±0.015	dB
Filter-gain stop band	0.55… 3.45 f_S	–58	dB
Filter group delay		18 / f_S	s

Figure 6-14 Frequency Response of Channel Interpolation Filter B

6.3.10.1.4.3 Interpolation Filter C

Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × f_S (corresponds to 80 kHz), more than sufficient for audio applications.

Table 6-17 Specification for DAC Interpolation Filter C

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
Filter-gain pass band	0 … 0.35 f_S	±0.03	dB
Filter-gain stop band	0.6… 1.4 f_S	–43	dB
Filter group delay		13 / f_S	s

Figure 6-15 Frequency Response of DAC Interpolation Filter C

6.3.10.2 DAC Digital-Volume Control

The DAC has a digital-volume control block which implements programmable gain. Each channel has an independent volume control that can be varied from 24 dB to –63.5 dB in 0.5-dB steps. The mono-channel DAC volume is controlled by writing to page 0 / register 65, bits D7–D0. The right-channel DAC volume can be controlled by writing to page 0 / register 66, bits D7–D0. DAC muting and setting up a master gain control to control mono-channel occurs by writing to page 0 / register 64, bits D3–D0. The gain is implemented with a soft-stepping algorithm, which only changes the actual volume by 0.125 dB per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping is slowed to one step per two input samples by writing to page 0 / register 63, bits D1–D0. Note that the default source for volume-control level settings is control by register writes (page 0 / register 65 and page 0 / register 66 to control volume). Use of the VOL/MICDET pin to control the DAC volume is ignored until the volume control source selected has been changed to pin control (page 0 / register 116, bit D7 = 1). This functionality is shown in .

During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This may be important if the host must mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the device provides a flag back to the host through a read-only register, page 0 / register 38, bit D4 for the left channel and bit D0 for the right channel. This information alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level. The soft-stepping feature can be disabled by writing to page 0 / register 63, bits D1–D0.

If soft-stepping is enabled, the CODEC_CLKIN signal must be kept active until the DAC power-up flag is cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an internal oscillator.)

6.3.10.3 Volume Control Pin

The volume-control pin is not enabled by default but is enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63, bits D1–D0.

When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and updates the digital volume control by overwriting the current value of the volume control. The new volume setting which has been applied because of a change of voltage on the volume control pin is read on page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source is selected on page 0 / register 116, bit D6. The update rate is programmed on page 0 / register 116, bits D2–D0 for this 7-bit SAR ADC.

Table 6-18 lists The VOL/MICDET pin gain mapping.

Table 6-18 VOL/MICDET Pin Gain Mapping

VOL/MICDET PIN SAR OUTPUT	DIGITAL GAIN APPLIED
0	18 dB
1	17.5 dB
2	17 dB
:	:
35	0.5 dB
36	0.0 dB
37	–0.5 dB
:	:
89	–26.5 dB
90	–27 dB
91	–28 dB
:	:
125	–62 dB
126	–63 dB
127	Mute

Figure 6-16 shows the VOL/MICDET pin connection and functionality.

Figure 6-16 Digital Volume Controls for Beep Generator and DAC Play Data

As shown in Table 6-18, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB, and mute. However, if less maximum gain is required, then a smaller range of voltage must be applied to the VOL/MICDET pin. Applying a smaller range of voltage occurs by increasing the value of R2 relative to the value of (P1 + R1), so that more voltage is available at the bottom of P1. The circuit must also be designed such that for the values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed AVDD/2 (see Figure 6-16). The recommended values for R1, R2, and P1 for several maximum gains are shown in Table 6-19.

Table 6-19 VOL/MICDET Pin Gain Scaling

R1 (kΩ)	P1 (kΩ)	R2 (kΩ)	ADC VOLTAGE for AVDD = 3.3 V (V)	DIGITAL GAIN RANGE (dB)
25	25	0	0 to 1.65	18 to –63
33	25	7.68	0.386 to 1.642	3 to –63
34.8	25	9.76	0.463 to 1.649	0 to –63

6.3.10.4 Dynamic Range Compression

Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome this problem, dynamic range conpression (DRC) in the TLV320DAC3100 continuously monitors the output of the DAC digital volume control to detect its power level relative to 0 dBFS. When the power level is low, DRC increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the ear as well as sounding louder during nominal periods.

The DRC functionality in the TLV320DAC3100 is implemented by a combination of processing blocks in the DAC channel as described in Section 6.3.10.1.2.

DRC can be disabled by writing to page 0 / register 68, bits D6–D5.

DRC typically works on the filtered version of the input signal. The input signals have no audio information at dc and extremely low frequencies; however, they can significantly influence the energy estimation function in the dynamic range compressor (the DRC). Also, most of the information about signal energy is concentrated in the low-frequency region of the input signal.

To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the DRC low-pass filter. These filters are implemented as first-order IIR filters given by

Equation 3. TLV320DAC3100 q-hhpf_las550.gif

Equation 4. TLV320DAC3100 q-hlpf_las550.gif

The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable through register write as given in Table 6-20.

Table 6-20 The DRC HPF and LPF Coefficients

COEFFICIENT	LOCATION
HPF N0	C71 page 9 / register 14 and page 9 / register 15
HPF N1	C72 page 9 / registers 16 and page 9 / register 17
HPF D1	C73 page 9 / registers 18 and page 9 / register 19
LPF N0	C74 page 9 / registers 20 and page 9 / register 21
LPF N1	C75 page 9 / registers 22 and page 9 / register 23
LPF D1	C76 page 9 / registers 24 and page 9 / register 25

The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_f_S, and a low-pass filter with a cutoff at 0.00033 × DAC_f_S.

The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The absolute value of the DRC LPF filter is used for energy estimation within the DRC.

The gain in the DAC digital volume control is controlled by page 0 / register 65 and page 0 / register 66. When the DRC is enabled, the applied gain is a function of the digital volume control register setting and the output of the DRC.

The DRC parameters are described in sections that follow.

6.3.10.4.1 DRC Threshold

DRC threshold represents the level of the DAC playback signal at which the gain compression becomes active. The output of the digital volume control in the DAC is compared with the set threshold. The threshold value is programmable by writing to page 0 / register 68, bits D4–D2. The threshold value can be adjusted between –3 dBFS and –24 dBFS in steps of 3 dB. Keeping the DRC threshold value too high may not leave enough time for the DRC block to detect peaking signals, and can cause excessive distortion at the outputs. Keeping the DRC threshold value too low can limit the perceived loudness of the output signal.

The recommended DRC threshold value is –24 dB.

When the output signal exceeds the set DRC threshold, the interrupt flag bits at page 0 / register 44, bits D3–D2 are updated. These flag bits are sticky in nature, and are reset only after they are read back by the user. The non-sticky versions of the interrupt flags are also available at page 0 / register 46, bits D3–D2.

6.3.10.4.2 DRC Hysteresis

DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be programmed to represent values between 0 dB and 3 dB in steps of 1dB. DRC hysteresis provides a programmable window around the programmed DRC threshold that must be exceeded for the disabled DRC to become enabled, or the enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the DRC hysteresis is set to 3 dB, then if the gain compression in the DRC is inactive, the output of the DAC digital volume control must exceed –9 dBFS before gain compression due to the DRC is activated. Similarly, when the gain compression in the DRC is active, the output of the DAC digital volume control must fall below –15 dBFS for gain compression in the DRC to be deactivated. The DRC hysteresis feature prevents the rapid activation and de-activation of gain compression in the DRC in cases when the output of the DAC digital volume control rapidly fluctuates in a narrow region around the programmed DRC threshold. By programming the DRC hysteresis as 0 dB, the hysteresis action is disabled.

The recommended value of DRC hysteresis is 3 dB.

6.3.10.4.3 DRC Hold Time

DRC hold time is intended to slow the start of decay for a specified period of time in response to a decrease in energy level. To minimize audible artifacts, TI recommends to set the DRC hold time to 0 through programming page 0 / register 69, bits D6–D3 = 0000.

6.3.10.4.4 DRC Attack Rate

When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain applied in the DAC digital volume control is progressively reduced to avoid the signal from saturating the channel. This process of reducing the applied gain is called attack. To avoid audible artifacts, the gain is reduced slowly with a rate equaling the attack rate, programmable via page 0 / register 70, bits D7–D4. Attack rates can be programmed from 4-dB gain change per sample period to 1.2207e–5-dB gain change per sample period.

Attack rates should be programmed such that before the output of the DAC digital volume control can clip, the input signal should be sufficiently attenuated. High attack rates can cause audible artifacts, and too-slow attack rates may not be able to prevent the input signal from clipping.

The recommended DRC attack rate value is 1.9531e–4 dB per sample period.

6.3.10.4.5 DRC Decay Rate

When the DRC detects a reduction in output signal swing beyond the programmed DRC threshold, the DRC enters a decay state, where the applied gain in the digital-volume control is gradually increased to programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the decay rate programmed through page 0 / register 70, bits D3–D0. The decay rates can be programmed from 1.5625e–3 dB per sample period to 4.7683e–7 dB per sample period. If the decay rates are programmed too high, then sudden gain changes can cause audible artifacts. However, if it is programmed too slow, then the output may be perceived as too low for a long time after the peak signal has passed.

The recommended value of DRC decay rate is 2.4414e–5 dB per sample period.

6.3.10.4.6 Example Setup for DRC

Digital Vol gain = 12 dB
Threshold = –24 dB
Hysteresis = 3 dB
Hold time = 0 ms
Attack rate = 1.9531e–4 dB per sample period
Decay rate = 2.4414e–5 dB per sample period

Script

#Go to Page 0
w 30 00 00
#DAC => 12 db gain left
w 30 41 18
#DAC => 12 db gain right
w 30 42 18
#DAC => DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB
w 30 44 7F
#DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs'
w 30 45 00
#Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e-5 dB/Frame
w 30 46 B6
#Go to Page 9
w 30 00 09
#DRC HPF
w 30 0E 7F AB 80 55 7F 56
#DRC LPF W 30 14 00 11 00 11 7F DE

6.3.10.5 Headphone Detection

The TLV320DAC3100 device includes capability to monitor a headphone jack to determine if a plug has been inserted into the jack. Figure 6-17 shows the circuit configuration to enable this feature.

Figure 6-17 Jack Connections for Headphone Detection

Headphone Detection is enabled by programming page 0 / register 67, bit D1. In order to avoid false detections because of mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms to 512 ms is provided. This can be programmed through page 0 / register 67, bits D4–D2. For improved button-press detection, the debounce function has a range of 8 ms to 32 ms by programming page 0 / register 67, bits D1–D0.

The TLV320DAC3100 device also provides feedback to the user through register-readable flags, as well as an interrupt on the I/O pins when a button press or a headset insertion or removal event is detected. The value in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset insertion. Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is detected. Page 0 / register 44, bit D4 is a sticky flag which is set when the headset insertion or removal event is detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320DAC3100 device also provides an interrupt feature, whereby events can trigger the INT1, the INT2, or both interrupts. These interrupt events can be routed to one of the digital output pins. See Section 6.3.10.6 for details.

The TLV320DAC3100 device not only detects a headset insertion event, but also is able to distinguish between the different headsets inserted, such as stereo headphones or cellular headphones. After the headset-detection event, the user can read page 0 / register 67, bits D6–D5 to determine the type of headset inserted.

Table 6-21 Headphone Detection Block Registers

REGISTER	DESCRIPTION
Page 0 / register 67, bits D4–D2	Debounce programmability for headset detection
Page 0 / register 67, bits D1–D0	Debounce programmability for button press
Page 0 / register 44, bit D5	Sticky flag for button-press event
Page 0 / register 44, bit D4	Sticky flag for headset-insertion or -removal event
Page 0 / register 46, bit D5	Status flag for button-press event
Page 0 / register 46, bit D4	Status flag for headset insertion and removal
Page 0 / register 67, bits D6–D5	Flags for type of headset detected

The headset detection block requires AVDD to be powered. The headset detection feature in the TLV320DAC3100 device is achieved with very low power overhead, requiring less than 20 μA of additional current from the AVDD supply.

6.3.10.6 Interrupts

Some specific events in the TLV320DAC3100 device that can require host processor intervention are used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TLV320DAC3100 device has two defined interrupts, INT1 and INT2, that are configured by programming page 0 / register 48 and page 0 / register 49. A user can configure interrupts INT1 and INT2 to be triggered by one or many events, such as:

Headset detection
Button press
DAC DRC signal exceeding threshold
Overcurrent condition in headphone drivers and speaker drivers
Data overflow in the DAC processing blocks and filters

Each of these INT1 and INT2 interrupts can be routed to output pin GPIO1. These interrupt signals can either be configured as a single pulse or a series of pulses by programming page 0 / register 48, bit D0 and page 0 / register 49, bit D0. If the user configures the interrupts as a series of pulses, the events trigger the start of pulses that stop when the flag registers in page 0 / registers 44, 45, and 50 are read by the user to determine the cause of the interrupt.

6.3.10.7 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)

A special algorithm has been included in the digital signal processing block PRB_P25 for generating a digital sine-wave signal that is sent to the DAC. The digital sine-wave generator is also referred to as the beep generator in this document.

This functionality is intended for generating key-click sounds for user feedback. The sine-wave generator is very flexible (see Table 6-22) and is completely register programmable. Programming page 0 / register 71 through page 0 / register 79 (8 bits each) completely controls the functionality of this generator and allows for differentiating sounds.

The two registers used for programming the 16-bit sine-wave coefficient are page 0 / register 76 and page 0 / register 77. The two registers used for programming the 16-bit cosine-wave coefficient are page 0 / register 78 and page 0 / register 79. This coefficient resolution allows virtually any frequency of sine wave in the audio band to be generated, up to f_S/ 2.

The three registers used to control the length of the sine-burst waveform are page 0 / register 73 through page 0 / register 75. The resolution (bit) in the registers of the sine-burst length is one sample time, so this allows great control on the overall time of the sine-burst waveform. This 24-bit length timer supports
16 777 215 sample times. For example, if f_S is set at 48 kHz, and the register value equals 96 000 d (01 7700h), then the sine burst lasts exactly 2 seconds. The default settings for the tone generator, based on using a sample rate of 48 kHz, are 1-kHz (approximately) sine wave, with a sine-burst length of five cycles (5 ms).

Table 6-22 Beep Generator Register Locations (Page 0x00)

	LEFT BEEP CONTROL	RIGHT BEEP CONTROL	BEEP LENGTH			SINE		COSINE
	LEFT BEEP CONTROL	RIGHT BEEP CONTROL	MSB	MID	LSB	MSB	LSB	MSB	LSB
REGISTER	71	72	73	74	75	76	77	78	79

Table 6-23 Example Beep-Generator Settings for a 1000-Hz Tone

BEEP FREQUENCY		BEEP LENGTH (Cycles = 5)			SINE		COSINE		SAMPLE RATE
Hz		MSB (hex)	MID (hex)	LSB (hex)	MSB (hex)	LSB (hex)	MSB (hex)	LSB (hex)	Hz
1000⁽¹⁾		0	0	F0	10	B5	7E	E8	48 000

(1) These are the default settings.

Two registers are used to control the left sine-wave volume and the right sine-wave volume independently. The 6-bit digital volume control used allows level control of 2 dB to –61 dB in 1-dB steps. The left-channel volume is controlled by writing to page 0 / register 71, bits D5–D0. The right-channel volume is controlled by writing to page 0, register 72, bits D5–D0. A master volume control that controls the left and right channels of the beep generator are set up by writing to page 0 / register 72, bits D7–D6. The default volume control setting is 2 dB, which provides the maximum tone-generator output level.

For generating other tones, the three tone-generator coefficients are found by running the following script using MATLAB™ :

Sine = dec2hex(round(sin(2*π*Fin/Fs)*2^15))
Cosine = dec2hex(round(cos(2*π*Fin/Fs)*2^15)) 
Beep Length = dec2hex(floor(Fs*Cycle/Fin))

where,

Fin = Beep frequency desired
Fs = Sample rate
Cycle = Number of beep (sine wave) cycles that are required
dec2hex = Decimal to hexadecimal conversion function

NOTES:

Fin must be less than Fs / 4.
For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused MSBs must be written as 0s.
For the beep-length values, if number of bits is less than the full 24-bit value, then the unused MSBs must be written as 0s.

Following the beep-volume control is a digital mixer that mixes in a playback data stream whose level has already been set by the DAC volume control. Therefore, once the key-click volume level is set, the key-click volume is not affected by the DAC volume control, which is the main control available to the end user. shows this functionality.

Following the DAC, the signal can be further scaled by the analog output volume control and power-amplifier level control.

To insert a beep in the middle of an already-playing signal over DAC, use the following sequence.

Before the beep is desired, program the desired beep frequency, volume, and length in the configuration registers. When a beep is desired, use the example configuration script.


w 30 00 00           # change to Page 0
w 30 40 0C           # mute DACs
f  30 26 xxx1xxx1    # wait for DAC gain flag to be set
w 30 0B 02           # power down NDAC divider
w 30 47 80           # enable beep generator with left channel volume = 0dB, volume level could
                     # be different as per requirement
w 30 0B 82           # power up NDAC divider, in this specific example NDAC = 2, but NDAC could
                     # be different value as per overall setup
w 30 40 00           # un-mute DAC to resume playing audio

Note that in this scheme the audio signal on the DAC is temporarily muted to enable beep generation. Because powering down of NDAC clock divider is required, do not use the DAC_CLK or DAC_MOD_CLK for generation of I²S clocks.

6.3.10.8 Programming DAC Digital Filter Coefficients

The digital filter coefficients must be programmed through the I²C interface. All digital filtering for the DAC signal path must be loaded into the RAM before the DAC is powered on. Note that default ALLPASS filter coefficients for programmable biquads are located in boot ROM. The boot ROM automatically loads the default values into the RAM following a hardware reset (toggling the RESET pin) or after a software reset. After resetting the device, loading boot ROM coefficients into the digital filters requires 100 μs of programming time. During this time, reading or writing to page 8 through page 15 for updating DAC filter coefficient values is not permitted. The DAC should not be powered up until after all of the DAC configurations have been done by the system microprocessor.

6.3.10.9 Updating DAC Digital Filter Coefficients During PLAY

When it is required to update the DAC digital filter coefficients or beep generator during play, care must be taken to avoid click and pop noise or even a possible oscillation noise. These artifacts can occur if the DAC coefficients are updated without following the proper update sequence. The correct sequence is shown in Figure 6-18. The values for times listed in Figure 6-18 are conservative and should be used for software purposes.

There is also an adaptive mode, in which DAC coefficients can be updated while the DAC is on. For details, see Section 6.3.10.1.3.

Figure 6-18 Example Flow For Updating DAC Digital Filter Coefficients During Play

6.3.10.10 Digital Mixing and Routing

The TLV320DAC3100 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the digital audio data. This arrangement of digital mixers allows independent volume control for both the playback data and the key-click sound. The first set of mixers can be used to make monaural signals from left and right audio data, or they can even be used to swap channels to the DAC. This function is accomplished by selecting left audio data for the right DAC input, and right data for the left DAC input. The second set of mixers provides mixing of the audio data stream and the key-click sound. The digital routing can be configured by writing to page 0 / register 63, bits D5–D4 for the left channel and bits D3–D2 for the right channel.

Because the key-click function uses the digital signal processing block, the CODEC_CLKIN, DAC, analog volume control, and output driver must be powered on for the key-click sound to occur.

6.3.10.11 Analog Audio Routing

The TLV320DAC3100 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can operate at the same time while playing at different volume levels. The TLV320DAC3100 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All analog outputs other than the selected ones can be powered down for optimal power consumption.

6.3.10.11.1 Analog Output Volume Control

The output volume control fine tunes the level of the mixer amplifier signal supplied to the headphone driver or the speaker driver. This architecture supports separate and concurrent volume levels for each of the four output drivers. This volume control is also used as part of the output pop-noise reduction scheme. This feature is available even if the DAC is powered down.

6.3.10.11.2 Headphone Analog-Output Volume Control

For the headphone outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for most of the useful range plus mute, which is shown in Table 6-24. This volume control includes soft-stepping logic. Routing the left-channel DAC output signal to the left-channel analog volume control occurs by writing to page 1 / register 35, bit D6. Routing the right-channel DAC output signal to the right-channel analog volume control occurs by writing to page 1 / register 35, bit D2.

Changing the left-channel analog volume for the headphone is controlled by writing to page 1 / register 36, bits D6–D0. Changing the right-channel analog volume for the headphone is controlled by writing to page 1 / register 37, bits D6–D0. Routing the signal from the output of the left-channel analog volume control to the input of the left-channel headphone power amplifier occurs by writing to page 1 / register 36, bit D7. Routing the signal from the output of the right-channel analog volume control to the input of the right-channel headphone power amplifier occurs by writing to page 1 / register 37, bit D7.

The analog volume-control soft-stepping time is based on the setting in page 0 / register 63, bits D1–D0.

Table 6-24 Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1)⁽¹⁾

REGISTER VALUE (D6–D0)	ANALOG GAIN (dB)	REGISTER VALUE (D6–D0)	ANALOG GAIN (dB)	REGISTER VALUE (D6–D0)	ANALOG GAIN (dB)	REGISTER VALUE (D6–D0)	ANALOG GAIN (dB)
0	0	30	–15	60	–30.1	90	–45.2
1	–0.5	31	–15.5	61	–30.6	91	–45.8
2	–1	32	–16	62	–31.1	92	–46.2
3	–1.5	33	–16.5	63	–31.6	93	–46.7
4	–2	34	–17	64	–32.1	94	–47.4
5	–2.5	35	–17.5	65	–32.6	95	–47.9
6	–3	36	–18.1	66	–33.1	96	–48.2
7	–3.5	37	–18.6	67	–33.6	97	–48.7
8	–4	38	–19.1	68	–34.1	98	–49.3
9	–4.5	39	–19.6	69	–34.6	99	–50
10	–5	40	–20.1	70	–35.2	100	–50.3
11	–5.5	41	–20.6	71	–35.7	101	–51
12	–6	42	–21.1	72	–36.2	102	–51.4
13	–6.5	43	–21.6	73	–36.7	103	–51.8
14	–7	44	–22.1	74	–37.2	104	–52.2
15	–7.5	45	–22.6	75	–37.7	105	–52.7
16	–8	46	–23.1	76	–38.2	106	–53.7
17	–8.5	47	–23.6	77	–38.7	107	–54.2
18	–9	48	–24.1	78	–39.2	108	–55.3
19	–9.5	49	–24.6	79	–39.7	109	–56.7
20	–10	50	–25.1	80	–40.2	110	–58.3
21	–10.5	51	–25.6	81	–40.7	111	–60.2
22	–11	52	–26.1	82	–41.2	112	–62.7
23	–11.5	53	–26.6	83	–41.7	113	–64.3
24	–12	54	–27.1	84	–42.1	114	–66.2
25	–12.5	55	–27.6	85	–42.7	115	–68.7
26	–13	56	–28.1	86	–43.2	116	–72.2
27	–13.5	57	–28.6	87	–43.8	117–127	–78.3
28	–14	58	–29.1	88	–44.3
29	–14.5	59	–29.6	89	–44.8

(1) Mute when D7 = 0 and D6–D0 = 127 (0x7F).

6.3.10.11.3 Class-D Speaker Analog Output Volume Control

For the mono speaker outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for most of the useful range plus mute, as seen in Table 6-24. The implementation includes soft-stepping logic.

Routing the left-channel DAC output signal to the left-channel analog volume control is done by writing to page 1 / register 35, bit D6. Routing the right-channel DAC output signal to the right-channel analog volume control is done by writing to page 1 / register 35, bit D2. Changing the left-channel analog volume for the speaker is controlled by writing to page 1 / register 38, bits D6–D0. Changing the right-channel analog volume for the speaker is controlled by writing to page 1 / register 39, bits D6–D0.

Routing the signal from the output of the left-channel analog volume control to the input of the mono speaker amplifier is done by writing to page 1 / register 38, bit D7.

The analog volume-control soft-stepping time is based on the setting in page 0 / register 63, bits D1–D0.

6.3.10.12 Analog Outputs

Various analog routings are supported for playback. All the options can be conveniently viewed on the functional block diagram, .

6.3.10.12.1 Headphone Drivers

The TLV320DAC3100 device features a stereo headphone driver (HPL and HPR) that delivers up to 30 mW per channel, at 3.3-V supply voltage, into a 16-Ω load. The headphones are used in a single-ended configuration where an ac-coupling capacitor (dc-blocking) is connected between the device output pins and the headphones. The headphone driver also supports 32-Ω and 10-kΩ loads without changing any control register settings.

The headphone drivers can be configured to optimize the power consumption in the lineout-drive mode by writing 11 to page 1 / register 44, bits D2–D1.

The output common mode of the headphone and lineout drivers is programmed to 1.35 V, 1.5 V, 1.65 V, or 1.8 V by setting page 1 / register 31, bits D4–D3. Set the common-mode voltage to ≤ AVDD / 2.

The left headphone driver can be powered on by writing to page 1 / register 31, bit D7. The right headphone driver can be powered on by writing to page 1 / register 31, bit D6. The left-output driver gain can be controlled by writing to page 1 / register 40, bits D6–D3, and it can be muted by writing to page 1 / register 40, bit D2. The right-output driver gain can be controlled by writing to page 1 / register 41, bits D6–D3, and it can be muted by writing to page 1 / register 41, bit D2.

The TLV320DAC3100 device has a short-circuit protection feature for the headphone drivers, which is always enabled to provide protection. The output condition of the headphone driver during short circuit is programmed by writing to page 1 / register 31, bit D1. If D1 = 0 when a short circuit is detected, the device limits the maximum current to the load. If D1 = 1 when a short circuit is detected, the device powers down the output driver. The default condition for headphones is the current-limiting mode. In case of a short circuit on either channel, the output is disabled and a status flag is provided as read-only bits on page 1 / register 31, bit D0. If shutdown mode is enabled, then as soon as the short circuit is detected, page 1 / register 31, bit D7 (for HPL) or page 1 / register 31, bit D6, or both (for HPR) clear automatically. Next, the device requires a reset to re-enable the output stage. Resetting occurs in two ways. First, the device master reset can be used, which requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated headphone power-stage reset can also be used to re-enable the output stage, and that keeps all of the other device settings. The headphone power stage reset occurs by setting page 1 / register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for HPR. If the fault condition has been removed, then the device returns to normal operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three times) is not recommended, as this could lead to overheating.

6.3.10.12.2 Speaker Drivers

The TLV320DAC3100 device has an integrated class-D mono speaker driver (SPKP/SPKM) capable of driving a 4-Ω or an 8-Ω differential load. The speaker driver can be powered directly from the battery supply (2.7 V to 5.5 V) on the SPKVDD pins; however, the voltage (including spike voltage) must be limited below the absolute-maximum voltage of 6 V.

The speaker driver is capable of supplying 2.5 W with a 5.5-V power supply (4-Ω load). Through the use of digital mixing, the device can connect one or both digital audio playback data channels to the speaker driver.

The mono class-D speaker driver can be powered on by writing to page 1 / register 32, bit D7. The mono output-driver gain can be controlled by writing to page 1 / register 42, bits D4–D3, and it can be muted by writing to page 1 / register 42, bit D2.

The TLV320DAC3100 device has a short-circuit protection feature for the speaker drivers that is always enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current limiting is not an available option for the higher-current speaker driver output stage.) In case of a short circuit on either channel, the output is disabled and a status flag is provided as a read-only bit on page 1 / register 32, bit D0.

If shutdown occurs because of an overcurrent condition, then the device requires a reset to re-enable the output stage. Resetting occurs in two ways. First, the device master reset can be used, which requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device settings. The speaker power-stage reset occurs by setting page 1 / register 32, bit D7 SPKP and SPKM. If the fault condition has been removed, then the device returns to normal operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three times) is not recommended as this could lead to overheating.

To minimize battery current leakage, the SPKVDD and SPKVDD voltage levels must not be less than the AVDD voltage level.

The TLV320DAC3100 device has a thermal protection (OTP) feature for the speaker drivers which is always enabled to provide protection. If the device overheats, then the output stops switching. When the device cools down, the device resumes switching. An overtemperature status flag is provided as a read-only bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die temperature can be controlled at the system or board level, then overtemperature does not occur.

6.3.10.13 Audio-Output Stage-Power Configurations

After the device has been configured (following a RESET) and the circuitry has been powered up, the audio output stage can be powered up and powered down by register control.

These functions soft-start automatically. By using these register controls, it is possible to control these three output-stage configurations independently.

See Table 6-25 for register control of audio output stage power configurations.

Table 6-25 Audio-Output Stage-Power Configurations

AUDIO OUTPUT PINS	DESIRED FUNCTION	PAGE 1 / REGISTER, BIT VALUES
HPL	Power down HPL driver	Page 1 / register 31, bit D7 = 0
HPL	Power up HPL driver	Page 1 / register 31, bit D7 = 1
HPR	Power down HPR driver	Page 1 / register 31, bit D6 = 0
HPR	Power up HPR driver	Page 1 / register 31, bit D6 = 1
SPKP / SPKM	Power down mono class-D drivers	Page 1 / register 32, bit D7 = 0
SPKP / SPKM	Power up mono class-D drivers	Page 1 / register 32, bit D7 = 1

6.3.10.14 DAC Setup

The following paragraphs are intended to guide a user through the steps necessary to configure the TLV320DAC3100.

Step 1

The system clock source (master clock) and the targeted DAC sampling frequency must be identified.

Depending on the targeted performance, the decimation filter type (A, B, or C) and DOSR value can be determined:

Filter A should be used for 48-kHz high-performance operation; DOSR must be a multiple of 8.
Filter B should be used for up to 96-kHz operations; DOSR must be a multiple of 4.
Filter C should be used for up to 192-kHz operations; DOSR must be a multiple of 2.

In all cases, DOSR is limited in its range by the following condition:

2.8 MHz < DOSR × DAC_f_S < 6.2 MHz

Based on the identified filter type and the required signal-processing capabilities, the appropriate processing block can be determined from the list of available processing blocks (PRB_P1 to PRB_P25).

Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock-divider values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of flexibility.

In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by MDAC, NDAC, and DOSR must be equal to the DAC sampling rate, DAC_f_S. The CODEC_CLKIN clock signal is shared with the DAC clock-generation block.

CODEC_CLKIN = NDAC × MDAC × DOSR × DAC_f_S

To a large degree, NDAC and MDAC can be chosen independently in the range of 1 to 128. In general, NDAC should be as large as possible as long as the following condition can still be met:

MDAC × DOSR / 32 ≥ RC

RC is a function of the chosen processing block and is listed in Table 6-11.

The common-mode voltage setting of the device is determined by the available analog power supply.

At this point, the following device-specific parameters are known: PRB_Px, DOSR, NDAC, MDAC, input and output common-mode values. If the PLL is used, the PLL parameters P, J, D, and R are determined as well.

Step 2

Setting up the device via register programming:

The following list gives an example sequence of items that must be executed in the time between powering the device up and reading data from the device. Note that there are other valid sequences, depending on which features are used.

Define starting point:
1. Power up applicable external power supplies
2. Set register page to 0
3. Initiate SW reset
Program clock settings
1. Program PLL clock dividers P, J, D, and R (if PLL is used)
2. Power up PLL (if PLL is used)
3. Program and power up NDAC
4. Program and power up MDAC
5. Program OSR value
6. Program I²S word length if required (16, 20, 24, or 32 bits)
7. Program the processing block to be used
8. Micellaneous page 0 controls
Program analog blocks
1. Set register page to 1
2. Program common-mode voltage
3. Program headphone-specific de-pop settings (in case headphone driver is used)
4. Program routing of DAC output to the output amplifier (headphone/lineout or speaker)
5. Unmute and set gain of output drivers
6. Power up output drivers
Apply waiting time determined by the de-pop settings and the soft-stepping settings of the driver gain, or poll page 1 / register 63
Power up DAC
1. Set register page to 0
2. Power up DAC channels and set digital gain
3. Unmute digital volume control

A detailed example can be found in Section 6.3.10.15.

6.3.10.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs

A typical EVM I²C register control script follows to show how to set up the TLV320DAC3100 in playback mode with f_S = 44.1 kHz and MCLK = 11.2896 MHz.



# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY

#               # ==> comment delimiter

#
# The following list gives an example sequence of items that must be executed in the time 
# between powering the # device up and reading data from the device. Note that there are 
# other valid sequences depending on which features are used.
# 1. Define starting point:
#    (a) Power up applicable external hardware power supplies
#    (b) Set register page to 0
#
w 30 00 00
#
#    (c) Initiate SW reset (PLL is powered off as part of reset)
#
w 30 01 01
#
# 2. Program clock settings
#    (a) Program PLL clock dividers P, J, D, R (if PLL is used)
#
# PLL_clkin = MCLK,codec_clkin = PLL_CLK
w 30 04 03
# J = 8
w 30 06 08
# D = 0000, D(13:8) = 0, D(7:0) = 0
w 30 07 00 00
#
#    (b) Power up PLL (if PLL is used)
# PLL Power up, P = 1, R = 1
#
w 30 05 91
#
#    (c) Program and power up NDAC
#
# NDAC is powered up and set to 8
w 30 0B 88
#
#    (d) Program and power up MDAC
#
# MDAC is powered up and set to 2
w 30 0C 82
#
#    (e) Program OSR value
#
# DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
w 30 0D 00 80
#
#    (f) Program I2S word length if required (16, 20, 24, 32 bits)
#        and master mode (BCLK and WCLK are outputs)
#
# mode is i2s, wordlength is 16, slave mode
w 30 1B 00
#    (g) Program the processing block to be used
#
# Select Processing Block PRB_P11
w 30 3C 0B
w 30 00 08
w 30 01 04
w 30 00 00
#
#    (h) Miscellaneous page 0 controls
#
# DAC => volume control thru pin disable
w 30 74 00
# 3. Program analog blocks
#
#    (a) Set register page to 1
#
w 30 00 01
#
#    (b) Program common-mode voltage (defalut = 1.35 V)
#
w 30 1F 04
#
#    (c) Program headphone-specific depop settings (in case headphone driver is used)
#
# De-pop, Power on = 800 ms, Step time = 4 ms
w 30 21 4E
#
#    (d) Program routing of DAC output to the output amplifier (headphone/lineout or speaker)
#
# LDAC routed to HPL out, RDAC routed to HPR out
w 30 23 44
#
#    (e) Unmute and set gain of output driver
#
# Unmute HPL, set gain = 0 db
w 30 28 06
# Unmute HPR, set gain = 0 dB
w 30 29 06
# Unmute Class-D, set gain = 18 dB
w 30 2A 1C
#
#    (f) Power up output drivers
#
# HPL and HPR powered up
w 30 1F C2
# Power-up Class-D driver
w 30 20 86
# Enable HPL output analog volume, set = -9 dB
w 30 24 92
# Enable HPR output analog volume, set = -9 dB
w 30 25 92
# Enable Class-D output analog volume, set = -9 dB
w 30 26 92
#
# 4. Apply waiting time determined by the de-pop settings and the soft-stepping settings 
#    of the driver gain or poll page 1 / register 63
#
# 5. Power up DAC
#    (a) Set register page to 0
#
w 30 00 00
#
#    (b) Power up DAC channels and set digital gain
#
# Powerup DAC left and right channels (soft step enabled)
w 30 3F D4
#
# DAC Left gain = -22 dB
w 30 41 D4
# DAC Right gain = -22 dB
w 30 42 D4
#
#    (c) Unmute digital volume control
#
# Unmute DAC left and right channels
w 30 40 00

6.3.11 CLOCK Generation and PLL

The TLV320DAC3100 device supports a wide range of options for generating clocks for the DAC section as well as interface and other control blocks as shown in Figure 6-19. The clocks for the DAC require a source reference clock. This clock is provided on a variety of device pins, such as the MCLK, BCLK, or GPIO1 pins. The source reference clock for the codec is chosen by programming the CODEC_CLKIN value on page 0 / register 4, bits D1–D0. The CODEC_CLKIN is then routed through highly-flexible clock dividers shown in Figure 6-19 to generate the various clocks required for the DAC. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO1, the TLV320DAC3100 device also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the TLV320DAC3100 device provides several programmable clock dividers to help achieve a variety of sampling rates for the DAC.

Figure 6-19 Clock Distribution Tree

Equation 5. TLV320DAC3100 eq_5-8_las659.gif

Table 6-26 CODEC CLKIN Clock Dividers

DIVIDER	BITS
NDAC	Page 0 / register 11, bits D6–D0
MDAC	Page 0 / register 12, bits D6–D0
DOSR	Page 0 / register 13, bits D1–D0 and page 0 / register 14, bits D7–D0

The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel, DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the device internally initiates a power-down sequence for proper shutdown. During this shutdown sequence, the NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not take place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 / register 37, bit D3. When both of the flags indicate power-down, the MDAC divider may be powered down, followed by the NDAC divider.

In general, for proper operation, all the root clock dividers must power down only after the child clock dividers have powered down.

The TLV320DAC3100 device also has options for routing some of the internal clocks to the GPIO1 pin to be used as general-purpose clocks in the system. The feature is shown in Figure 6-21.

Figure 6-20 BCLK Output Options

In the mode when the TLV320DAC3100 device is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1), the device is driven as the divided value of BDIV_CLKIN. The division value is programmed in page 0 / register 30, bits D6–D0 from 1 to 128. The BDIV_CLKIN is configurable to be one of DAC_CLK (DAC processing clock) or DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page 0 / register 29, bits D1–D0. Additionally, a general-purpose clock can be driven out on GPIO1.

This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. CDIV_CLKIN can also be programmed as one of the clocks among the list shown in Figure 6-21. This is controlled by programming the multiplexer in page 0 / register 25, bits D2–D0.

Figure 6-21 General-Purpose Clock Output Options

Table 6-27 Maximum TLV320DAC3100 Clock Frequencies

CLOCK	DVDD ≥ 1.65 V
CODEC_CLKIN	≤ 110 MHz
DAC_CLK (DAC processing clock)	≤ 49.152 MHz
DAC_MAC_CLK	≤ 49.152 MHz with DRC disabled ≤ 48 MHz with DRC enabled
DAC_MOD_CLK	6.758 MHz
DAC_f_S	0.192 MHz
BDIV_CLKIN	55 MHz
CDIV_CLKIN	100 MHz when M is odd 110 MHz when M is even

6.3.11.1 PLL

For lower power consumption, the best process is to derive the internal audio processing clocks using the simple dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing clocks then using the on-board PLL is necessary. The TLV320DAC3100 fractional PLL generates an internal master clock that produces the processing clocks required by the DAC. The programmability of this PLL allows operation from a wide variety of clocks that may be available in the system.

The PLL input supports clocks varying from 512 kHz to 20 MHz and is register-programmable to enable generation of the required sampling rates with fine resolution. The PLL turns on by writing to page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock, PLL_CLK, is given by Equation 6.

Equation 6. TLV320DAC3100 q-pll_las644.gif

where

R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)
J = 1, 2,3, … , 63, (page 0 / register 6, default value = 4)
D = 0, 1, 2, …, 9999 (page 0 / register 7 and page 0 / register 8, default value = 0)
P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1)

The PLL turns on through page 0 / register 5, bit D7. The variable P is programmed through page 0 / register 5, bits D6–D4. The variable R is programmed through page 0 / register 5, bits D3–D0. The variable J is programmed through page 0 / register 6, bits D5–D0. The variable D is 14 bits and is programmed into two registers. The MSB portion is programmed through page 0 / register 7, bits D5–D0, and the LSB portion is programmed thrugh page 0 / register 8, bits D7–D0. For proper update of the D-divider value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. The new value of D does not take effect unless the write to page 0 / register 8 is complete.

When the PLL is enabled, the following conditions must be satisfied:

When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:

Equation 7. TLV320DAC3100 q-pll2_las644.gif

80 MHz ≤ (PLL_CLKIN × J.D. × R / P) ≤ 110 MHz

4 ≤ R × J ≤ 259

When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:

Equation 8. TLV320DAC3100 q-pll3_las644.gif

80 MHz ≤ PLL_CLKIN × J.D. × R / P ≤ 110 MHz

R = 1

The PLL can power up independently from the DAC block, and can also be used as a general-purpose PLL by routing the PLL output to the GPIO output. After powering up the PLL, PLL_CLK is available typically after 10 ms.

The clocks for the codec and various signal processing blocks, CODEC_CLKIN, are generated from the MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).

If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last.

Table 6-28 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to achieve a sample rate f_S of either 44.1 kHz or 48 kHz.

Table 6-28 PLL Example Configurations

PLL_CLKIN (MHz)	PLLP	PLLR	PLLJ	PLLD	MDAC	NDAC	DOSR
f_S = 44.1 kHz
2.8224	1	3	10	0	3	5	128
5.6448	1	3	5	0	3	5	128
12	1	1	7	560	3	5	128
13	1	1	6	3504	6	3	104
16	1	1	5	2920	3	5	128
19.2	1	1	4	4100	3	5	128
48	4	1	7	560	3	5	128
f_S = 48 kHz
2.048	1	3	14	0	7	2	128
3.072	1	4	7	0	7	2	128
4.096	1	3	7	0	7	2	128
6.144	1	2	7	0	7	2	128
8.192	1	4	3	0	4	4	128
12	1	1	7	1680	7	2	128
16	1	1	5	3760	7	2	128
19.2	1	1	4	4800	7	2	128
48	4	1	7	1680	7	2	128

6.3.12 Timer

The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce logic, and interrupts. The MCLK divider must be set in such a way that the divider output is approximately 1 MHz for the timers to be closer to the programmed value.

Figure 6-22 Interval Timer Clock Selection

6.3.13 Digital Audio and Control Interface

6.3.13.1 Digital Audio Interface

Audio data is transferred between the host processor and the TLV320DAC3100 device through the digital audio data, serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified data options, support for I²S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master and slave configurability for each bus-clock line, and the ability to communicate with multiple devices within a system directly.

The audio bus of the TLV320DAC3100 device can be configured for left-justified or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either master or slave mode, for flexible connectivity to a wide variety of processors. The word clock defines the beginning of a frame, and can be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the DAC sampling frequency.

The bit clock is used to clock-in and clock-out the digital audio data across the serial bus. When in master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0 / register 30 (see Figure 6-19). The number of bit-clock pulses in a frame can require adjustment to accommodate various word lengths as well as to support the case when multiple TLV320DAC3100s share the same audio bus.

The TLV320DAC3100 device also includes a feature to offset the position of start-of-data transfer with respect to the word clock. This offset is controlled in terms of number of bit-clocks and can be programmed in page 0 / register 28.

The TLV320DAC3100 device also has the feature of inverting the polarity of the bit clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. This can be configured through page 0 / register 29, bit D3.

By default, when the word clocks and bit clocks are generated by the TLV320DAC3100 device, these clocks are active only when the DACis powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit clocks can be active even when the codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word clocks or bit clocks are used in the system as general-purpose clocks.

6.3.13.1.1 Right-Justified Mode

The audio interface of the TLV320DAC3100 can enter the right-justified mode by programming page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

Figure 6-23 Timing Diagram for Right-Justified Mode

For the right-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data.

6.3.13.1.2 Left-Justified Mode

The audio interface of the TLV320DAC3100 can enter the left-justified mode by programming page 0 / register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

Figure 6-24 Timing Diagram for Left-Justified Mode

Figure 6-25 Timing Diagram for Left-Justified Mode With Offset = 1

Figure 6-26 Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock

For the left-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data.

6.3.13.1.3 I²S Mode

The audio interface of the TLV320DAC3100 device enters I²S mode by programming page 0 / register 27, bits D7–D6 = to 00. In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 6-27 Timing Diagram for I²S Mode

Figure 6-28 Timing Diagram for I²S Mode With Offset = 2

Figure 6-29 Timing Diagram for I²S Mode With Offset = 0 and Bit Clock Inverted

For I²S mode, the number of bit clocks per channel should be greater-than or equal-to the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data.

6.3.13.1.4 DSP Mode

The audio interface of the TLV320DAC3100 can enter DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 6-30 Timing Diagram for DSP Mode

Figure 6-31 Timing Diagram for DSP Mode With Offset = 1

Figure 6-32 Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted

For the DSP mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data.

6.3.13.2 Primary and Secondary Digital Audio Interface Selection

The audio serial interface on the TLV320DAC3100 has extensive I/O control to allow communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections. shows the primary and secondary audio interface selection and registers. Figure 6-33 is a high-level diagram showing the general signal flow and multiplexing for the primary and secondary audio interfaces.

Table 6-29 Primary and Secondary Audio Interface Selection

DESIRED PIN FUNCTION	POSSIBLE PINS	PAGE 0 REGISTERS	COMMENT
Primary WCLK (OUT)	WCLK	R27/D2 = 1	Primary WCLK is output from codec
Primary WCLK (OUT)	WCLK	R33/D5–D4	Select source of primary WCLK (DAC_fs or secondary WCLK)
Primary WCLK (IN)	WCLK	R27/D2 = 0	Primary WCLK is input to codec
Primary BCLK (OUT)	BCLK	R27/D3 = 1	Primary BCLK is output from codec
Primary BCLK (OUT)	BCLK	R33/D7	Select source of primary WCLK (internal BCLK or secondary BCLK)
Primary BCLK (IN)	BCLK	R27/D3 = 0	Primary BCLK is input to codec
Primary DIN (IN)	DIN	R32/D0	Select DIN to internal interface (0 = primary DIN; 1 = secondary DIN)
Secondary WCLK (OUT)	GPIO1	R31/D4–D2 = 000	Secondary WCLK obtained from GPIO1 pin
		R51/D5–D2 = 1001	GPIO1 is secondary WCLK output.
		R33/D3–D2	Select source of Secondary WCLK (DAC_f_S or primary WCLK)
Secondary WCLK (IN)	GPIO1	R31/D4–D2 = 000	Secondary WCLK obtained from GPIO1 pin
Secondary WCLK (IN)	GPIO1	R51/D5–D2 = 0001	GPIO1 enabled as secondary input
Secondary BCLK (OUT)	GPIO1	R31/D7–D5 = 000	Secondary BCLK obtained from GPIO1 pin
		R51/D5–D2 = 1000	GPIO1 is secondary BCLK output.
		R33/D6	Select source of secondary BCLK (primary BCLK or internal BCLK)
Secondary BCLK (IN)	GPIO1	R31/D7–D5 = 000	Secondary BCLK obtained from GPIO1 pin
Secondary BCLK (IN)	GPIO1	R51/D5–D2 = 0001	GPIO1 enabled as secondary input
Secondary DIN (IN)	GPIO1	R31/D1–D0 = 00	Secondary DIN obtained from GPIO1 pin
Secondary DIN (IN)	GPIO1	R51/D5–D2 = 0001	GPIO1 enabled as secondary input

Figure 6-33 Audio Serial Interface Multiplexing

6.3.13.3 Control Interface

The TLV320DAC3100 control interface supports the I²C communication protocol.

6.3.13.3.1 I²C Control Mode

The TLV320DAC3100 supports the I²C control protocol, and responds to the I²C address of 0011 000. I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Communication on the I²C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320DAC3100 can only act as a slave device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock. All data is transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero, while a HIGH indicates the bit is one).

Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start communication on the bus. Generally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or the counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that selects the slave device for communication. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I²C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it is to read from or write to the slave device.

Every byte transmitted on the I²C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (Remember that the master always drives the clock line.)

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address the device, the master receives a not-acknowledge because no device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320DAC3100 can also respond to and acknowledge a general call, which consists of the master issuing a command with a slave address byte of 00h. This feature is disabled by default, but can be enabled through page 0 / register 34, bit D5.

Figure 6-34 I²C Write

Figure 6-35 I²C Read

In the case of an I²C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Similarly, in the case of an I²C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of the SDA bus and transmits for the next eight clocks the data of the next incremental register.

6.4 Register Map

6.4.1 TLV320DAC3100 Register Map

All features on this device are addressed using the I²C bus. All of the writable registers can be read back. However, some registers contain status information or data, and are only available for reading.

The TLV320DAC3100 device contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device. The pages defined for the TLV320DAC3100 device are 0, 1, 3, 8–9, 12–13 (DAC coefficient pages). Page 0 is the default home page after RESET. Page control occurs by writing a new page value into register 0 of the current page.

The control registers for the TLV320DAC3100 device are described in detail as follows. All registers are 8 bits in width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.

Pages 0, 1, 3, 8–9, and 12–13 are available for use. All other pages and registers are reserved. Do not read from or write to reserved pages and registers. Also, do not write other than the reset values for the reserved bits and read-only bits of non-reserved registers; otherwise, device functionality failure can occur.

NOTE

Note that the page and register numbers are shown in decimal format. For use in microcode, these decimal values may need to be converted to hexadecimal format. For convenience, the register numbers are shown in both formats, whereas the page numbers are shown only in decimal format.

Table 6-30 Summary of Register Map

PAGE NUMBER	DESCRIPTION
0	Page 0 is the default page on power up. Configuration for serial interface, digital I/O, and other circuitry.
1	Configuration for DAC, output drivers, volume controls, and other circuitry.
3	Register 16 controls the MCLK divider that controls the interrupt pulse duration, debounce timing, and detection-block clock.
8–9	DAC filter and DRC coefficients (buffer A)
12–13	DAC filter and DRC coefficients (buffer B)

6.4.2 Registers

6.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs

Table 6-31 Page 0 / Register 0 (0x00): Page Control Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	0000 0000: Page 0 selected 0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected

Table 6-32 Page 0 / Register 1 (0x01): Software Reset

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D1	R/W	0000 000	Reserved. Write only zeros to these bits.
D0	R/W	0	0: Don't care 1: Self-clearing software reset for control register

Table 6-33 Page 0 / Register 2 (0x02): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not write to this register.

Table 6-34 Page 0 / Register 3 (0x03): OT FLAG

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7-D2	R	XXXX XX	Reserved. Do not write to these bits.
D1	R	1	0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up 1: Normal operation
D0	R/W	X	Reserved. Do not write to these bits.

Table 6-35 Page 0 / Register 4 (0x04): Clock-Gen Muxing⁽¹⁾

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D4	R/W	0000	Reserved. Write only zeros to these bits.
D3–D2	R/W	00	00: PLL_CLKIN = MCLK (device pin) 01: PLL_CLKIN = BCLK (device pin) 10: PLL_CLKIN = GPIO1 (device pin) 11: PLL_CLKIN = DIN (can be used for the system where DAC is not used)
D1–D0	R/W	00	00: CODEC_CLKIN = MCLK (device pin) 01: CODEC_CLKIN = BCLK (device pin) 10: CODEC_CLKIN = GPIO1 (device pin) 11: CODEC_CLKIN = PLL_CLK (generated on-chip)

(1) See Section 6.3.11 for more details on clock generation mutiplexing and dividers.

Table 6-36 Page 0 / Register 5 (0x05): PLL P and R Values

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: PLL is powered down. 1: PLL is powered up.
D6–D4	R/W	001	000: PLL divider P = 8 001: PLL divider P = 1 010: PLL divider P = 2 ... 110: PLL divider P = 6 111: PLL divider P = 7
D3–D0	R/W	0001	0000: PLL multiplier R = 16 0001: PLL multiplier R = 1 0010: PLL multiplier R = 2 ... 1110: PLL multiplier R = 14 1111: PLL multiplier R = 15

Table 6-37 Page 0 / Register 6 (0x06): PLL J-Value

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D6	R/W	00	Reserved. Write only zeros to these bits.
D5–D0	R/W	00 0100	00 0000: Do not use (reserved) 00 0001: PLL multiplier J = 1 00 0010: PLL multiplier J = 2 ... 11 1110: PLL multiplier J = 62 11 1111: PLL multiplier J = 63

Table 6-38 Page 0 / Register 7 (0x07): PLL D-Value MSB⁽¹⁾

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D6	R/W	00	Reserved. Write only zeros to these bits.
D5–D0	R/W	00 0000	PLL fractional multiplier D-value MSB bits D[13:8]

(1) Note that this register is updated only when Page 0 / Register 8 is written immediately after Page 0 / Register 7.

Table 6-39 Page 0 / Register 8 (0x08): PLL D-Value LSB⁽¹⁾

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	PLL fractional multiplier D-value LSB bits D[7:0]

(1) Note that Page 0 / Register 8 must be written immediately after Page 0 / Register 7.

Table 6-40 Page 0 / Register 9 (0x09) and Page 0 / Register 10 (0x0A): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not use

Table 6-41 Page 0 / Register 11 (0x0B): DAC NDAC_VAL

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: DAC NDAC divider is powered down. 1: DAC NDAC divider is powered up.
D6–D0	R/W	000 0001	000 0000: DAC NDAC divider = 128 000 0001: DAC NDAC divider = 1 000 0010: DAC NDAC divider = 2 ... 111 1110: DAC NDAC divider = 126 111 1111: DAC NDAC divider = 127

Table 6-42 Page 0 / Register 12 (0x0C): DAC MDAC_VAL

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: DAC MDAC divider is powered down. 1: DAC MDAC divider is powered up.
D6–D0	R/W	000 0001	000 0000: DAC MDAC divider = 128 000 0001: DAC MDAC divider = 1 000 0010: DAC MDAC divider = 2 ... 111 1110: DAC MDAC divider = 126 111 1111: DAC MDAC divider = 127

Table 6-43 Page 0 / Register 13 (0x0D): DAC DOSR_VAL MSB

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D2	R/W	0000 00	Reserved
D1–D0	R/W	00	DAC OSR value DOSR(9:8)

Table 6-44 Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB⁽²⁾⁽¹⁾

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	1000 0000	DAC OSR Value DOSR (7:0) 0000 0000: DAC OSR (7:0) = 1024 (MSB page 0 / register 13, bits D1–D0 = 00) 0000 0001: Reserved 0000 0010: DAC OSR (7:0) = 2 (MSB page 0 / register 13, bits D1–D0 = 00) ... 1111 1110: DAC OSR (7:0) = 1022 (MSB page 0 / register 13, bits D1–D0 = 11) 1111 1111: DAC OSR (7:0) = Reserved. Do not Use

(1) Note that Page 0 / Register 14 must be written to immediately after writing to Page 0 / Register 13.

(2) DAC OSR must be an integral multiple of the interpolation in the DAC miniDSP engine (specified in register 16). When using PRB modes, interpolation ratio is 8 while using Filter-A, 4 while using Filter-B and 2 while using Filter-C.

Table 6-45 Page 0 / Register 15 (0x0F) through Page 0 / Register 24 (0x18): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	XXXX XXXX	Reserved. Do not write to these registers.

Table 6-46 Page 0 / Register 25 (0x19): CLKOUT MUX

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D3	R/W	0000 0	Reserved
D2–D0	R/W	000	000: CDIV_CLKIN = MCLK (device pin) 001: CDIV_CLKIN = BCLK (device pin) 010: CDIV_CLKIN = DIN (can be used for the systems where DAC is not required) 011: CDIV_CLKIN = PLL_CLK (generated on-chip) 100: CDIV_CLKIN = DAC_CLK (DAC DSP clock - generated on-chip) 101: CDIV_CLKIN = DAC_MOD_CLK (generated on-chip) 110: Reserved 111: Reserved

Table 6-47 Page 0 / Register 26 (0x1A): CLKOUT M_VAL

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: CLKOUT M divider is powered down. 1: CLKOUT M divider is powered up.
D6–D0	R/W	000 0001	000 0000: CLKOUT divider M = 128 000 0001: CLKOUT divider M = 1 000 0010: CLKOUT divider M = 2 ... 111 1110: CLKOUT divider M = 126 111 1111: CLKOUT divider M = 127

Table 6-48 Page 0 / Register 27 (0x1B): Codec Interface Control 1

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D6	R/W	00	00: Codec interface = I²S 01: Codec Interface = DSP 10: Codec interface = RJF 11: Codec interface = LJF
D5–D4	R/W	00	00: Codec interface word length = 16 bits 01: Codec interface word length = 20 bits 10: Codec interface word length = 24 bits 11: Codec interface word length = 32 bits
D3	R/W	0	0: BCLK is input 1: BCLK is output
D2	R/W	0	0: WCLK is input 1: WCLK is output
D1–D0	R/W	0	Reserved

Table 6-49 Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	Offset (Measured With Respect to WCLK Rising Edge in DSP Mode) 0000 0000: Offset = 0 BCLKs 0000 0001: Offset = 1 BCLK 0000 0010: Offset = 2 BCLKs ... 1111 1110: Offset = 254 BCLKs 1111 1111: Offset = 255 BCLKs

Table 6-50 Page 0 / Register 29 (0x1D): Codec Interface Control 2

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D4	R/W	0000	Reserved
D3	R/W	0	0: BCLK is not inverted (valid for both primary and secondary BCLK) 1: BCLK is inverted (valid for both primary and secondary BCLK)
D2	R/W	0	BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary BCLK) 0: Disabled 1: Enabled
D1–D0	R/W	00	00: BDIV_CLKIN = DAC_CLK (generated on-chip) 01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip) 10: Reserved 11: Reserved

Table 6-51 Page 0 / Register 30 (0x1E): BCLK N_VAL

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: BCLK N-divider is powered down. 1: BCLK N-divider is powered up.
D6–D0	R/W	000 0001	000 0000: BCLK divider N = 128 000 0001: BCLK divider N = 1 000 0010: BCLK divider N = 2 ... 111 1110: BCLK divider N = 126 111 1111: BCLK divider N = 127

Table 6-52 Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D5	R/W	000	000: Secondary BCLK is obtained from GPIO1 pin. 001: Secondary BCLK is not obtained from the GPIO1 pin. 010: Reserved. 011: Reserved. 100: Reserved 101: Reserved. 110: Reserved. 111: Reserved
D4–D2	R/W	000	000: Secondary WCLK is obtained from GPIO1 pin. 001: Secondary WCLK is not obtained from the GPIO1 pin. 010: Reserved. 011: Reserved. 100: Reserved 101: Reserved. 110: Reserved. 111: Reserved
D1–D0	R/W	00	00: Secondary DIN is obtained from the GPIO1 pin. 01: Secondary DIN is not obtained from the GPIO1 pin. 10: Reserved. 11: Reserved

Table 6-53 Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D4	R/W	0000	Reserved
D3	R/W	0	0: Primary BCLK is fed to codec serial-interface and ClockGen blocks. 1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks.
D2	R/W	0	0: Primary WCLK is fed to codec serial-interface block. 1: Secondary WCLK is fed to codec serial-interface block.
D1	R/W	0	Reserved.
D0	R/W	0	0: Primary DIN is fed to codec serial-interface block. 1: Secondary DIN is fed to codec serial-interface block.

Table 6-54 Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Primary BCLK output = internally generated BCLK clock 1: Primary BCLK output = secondary BCLK
D6	R/W	0	0: Secondary BCLK output = primary BCLK 1: Secondary BCLK output = internally generated BCLK clock
D5–D4	R/W	00	00: Primary WCLK output = internally generated DAC_f_S 01: Reserved 10: Primary WCLK output = secondary WCLK 11: Reserved
D3–D2	R/W	00	00: Secondary WCLK output = primary WCLK 01: Secondary WCLK output = internally generated DAC_f_S clock 10: Reserved 11: Reserved
D1–D0	R/W	0	Reserved

Table 6-55 Page 0 / Register 34 (0x22): I²C Bus Condition

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D6	R/W	00	Reserved. Write only the reset value to these bits.
D5	R/W	0	0: I²C general-call address is ignored. 1: Device accepts I²C general-call address.
D4–D0	R/W	0 0000	Reserved. Write only zeros to these bits.

Table 6-56 Page 0 / Register 35 (0x23) and Page 0 / Register 36 (0x24): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	XXXX XXXX	Reserved. Write only zeros to these bits.

Table 6-57 Page 0 / Register 37 (0x25): DAC Flag Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R	0	0: Left-channel DAC powered down 1: Left-channel DAC powered up
D6	R	X	Reserved.
D5	R	0	0: HPL driver powered down 1: HPL driver powered up
D4	R	0	0: Left-channel class-D driver powered down 1: Left-channel class-D driver powered up
D3	R	0	0: Right-channel DAC powered down 1: Right-channel DAC powered up
D2	R	X	Reserved.
D1	R	0	0: HPR driver powered down 1: HPR driver powered up
D0	R	0	0: Right-channel class-D driver powered down 1: Right-channel class-D driver powered up

Table 6-58 Page 0 / Register 38 (0x26): DAC Flag Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D5	R	XXX	Reserved.
D4	R	0	0: Left-channel DAC PGA applied gain ≠ programmed gain 1: Left-channel DAC PGA applied gain = programmed gain
D3–D1	R	XXX	Reserved.
D0	R	0	0: Right-channel DAC PGA applied gain ≠ programmed gain 1: Right-channel DAC PGA applied gain = programmed gain

Table 6-59 Page 0 / Register 39 (0x27): Overflow Flags

BIT	READ/ WRITE	DESCRIPTION
D7⁽¹⁾	R	Left-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred.
D6⁽¹⁾	R	Right-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred.
D5⁽¹⁾	R	DAC Barrel Shifter Output Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred.
D4–D0	R	Reserved.

(1) Sticky flag bIt. These is a read-only bit. This bit is automatically cleared once it is read and is set only if the source trigger occurs again.

Table 6-60 Page 0 / Register 40 (0x28) Through Page 0 / Register 43 (0x2B): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not use

Table 6-61 Page 0 / Register 44 (0x2C): DAC Interrupt Flags (Sticky Bits)

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7⁽¹⁾	R	0	0: No short circuit is detected at HPL / left class-D driver. 1: Short circuit is detected at HPL / left class-D driver.
D6⁽¹⁾	R	0	0: No short circuit is detected at HPR / right class-D driver. 1: Short circuit is detected at HPR / right class-D driver.
D5⁽¹⁾	R	X	0: No headset button pressed. 1: Headset button pressed.
D4⁽¹⁾	R	X	0: No headset insertion or removal is detected. 1: Headset insertion or removal is detected.
D3⁽¹⁾	R	0	0: Left DAC signal power is less than or equal to the signal threshold of DRC. 1: Left DAC signal power is above the signal threshold of DRC.
D2⁽¹⁾	R	0	0: Right DAC signal power is less than or equal to the signal threshold of DRC. 1: Right DAC signal power is above the signal threshold of DRC.
D1-D0	R	0	Reserved.

Table 6-62 Page 0 / Register 45 (0x2D): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not use.

Table 6-63 Page 0 / Register 46 (0x2E): Interrupt Flags—DAC

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R	0	0: No short circuit detected at HPL / left class-D driver. 1: Short circuit detected at HPL / left class-D driver.
D6	R	0	0: No short circuit detected at HPR / right class-D driver 1: Short circuit detected at HPR / right class-D driver
D5	R	X	0: No headset button pressed. 1: Headset button pressed.
D4	R	X	0: Headset removal detected. 1: Headset insertion detected.
D3	R	0	0: Left DAC signal power is less than or equal to signal threshold of DRC. 1: Left DAC signal power is greater than signal threshold of DRC.
D2	R	0	0: Right DAC signal power is less than or equal to signal threshold of DRC. 1: Right DAC signal power is greater than signal threshold of DRC.
D1–D0	R	00	Reserved.

Table 6-64 Page 0 / Register 47 (0x2F): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	0000 0000	Reserved.

Table 6-65 Page 0 / Register 48 (0x30): INT1 Control Register

BIT	READ/ WRITE	DESCRIPTION
D7	R/W	0: Headset-insertion detect interrupt is not used in the generation of INT1 interrupt. 1: Headset-insertion detect interrupt is used in the generation of INT1 interrupt.
D6	R/W	0: Button-press detect interrupt is not used in the generation of INT1 interrupt. 1: Button-press detect interrupt is used in the generation of INT1 interrupt.
D5	R/W	0: DAC DRC signal-power interrupt is not used in the generation of INT1 interrupt. 1: DAC DRC signal-power interrupt is used in the generation of INT1 interrupt.
D4	R/W	Reserved
D3	R/W	0: Short-circuit interrupt is not used in the generation of INT1 interrupt. 1: Short-circuit interrupt is used in the generation of INT1 interrupt.
D2	R/W	0: DAC data overflow does not result in an INT1 interrupt. 1: DAC data overflow results in an INT1 interrupt.
D1	R/W	Reserved
D0	R/W	0: INT1 is only one pulse (active-high) of typical 2-ms duration. 1: INT1 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until flag register 44 is read by the user.

Table 6-66 Page 0 / Register 49 (0x31): INT2 Control Register

BIT	READ/ WRITE	DESCRIPTION
D7	R/W	0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt. 1: Headset-insertion detect interrupt is used in the generation of INT2 interrupt.
D6	R/W	0: Button-press detect interrupt is not used in the generation of INT2 interrupt. 1: Button-press detect interrupt is used in the generation of INT2 interrupt.
D5	R/W	0: DAC DRC signal-power interrupt is not used in the generation of INT2 interrupt. 1: DAC DRC signal-power interrupt is used in the generation of INT2 interrupt.
D4	R/W	Reserved
D3	R/W	0: Short-circuit interrupt is not used in the generation of INT2 interrupt. 1: Short-circuit interrupt is used in the generation of INT2 interrupt.
D2	R/W	0: DAC data overflow does not result in an INT2 interrupt. 1: DAC data overflow results in an INT2 interrupt.
D1	R/W	Reserved
D0	R/W	0: INT2 is only one pulse (active-high) of typical 2-ms duration. 1: INT2 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until flag register 44is read by the user.

Table 6-67 Page 0 / Register 50 (0x32): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7-D0	R	0000 0000	Reserved.Do not use.

Table 6-68 Page 0 / Register 51 (0x33): GPIO1 In/Out Pin Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D6	R/W	XX	Reserved. Do not write any value other than reset value.
D5–D2	R/W	0000	0000: GPIO1 disabled (input and output buffers powered down) 0001: GPIO1 is in input mode (can be used as secondary BCLK input, secondary WCLK input, secondary DIN input, or in ClockGen block). 0010: GPIO1 is used as general-purpose input (GPI). 0011: GPIO1 output = general-purpose output 0100: GPIO1 output = CLKOUT output 0101: GPIO1 output = INT1 output 0110: GPIO1 output = INT2 output 0111: Reserved 1000: GPIO1 output = secondary BCLK output for codec interface 1001: GPIO1 output = secondary WCLK output for codec interface 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: Reserved
D1	R	X	GPIO1 input buffer value
D0	R/W	0	0: GPIO1 general-purpose output value = 0 1: GPIO1 general-purpose output value = 1

Table 6-69 Page 0 / Register 52 (0x34): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not use.

Table 6-70 Page 0 / Register 53 (0x35): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	0000 0000	Reserved

Table 6-71 Page 0 / Register 54 (0x36): DIN (IN Pin) Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D3	R/W	0000 0	Reserved
D2–D1	R/W	01	00: DIN disabled (input buffer powered down) 01: DIN enabled (can be used as DIN for codec interface or into ClockGen block) 10: DIN is used as general-purpose input (GPI) 11: Reserved
D0	R	X	DIN input-buffer value

Table 6-72 Page 0 / Register 55 (0x37) through Page 0 / Register 59 (0x3B): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	XXXX XXXX	Reserved. Do not write to these registers.

Table 6-73 Page 0 / Register 60 (0x3C): DAC Processing Block Selection

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D5	R/W	000	Reserved. Write only default value.
D4–D0	R/W	00 0001	0 0000: Reserved. Do not use. 0 0001: DAC signal-processing block PRB_P1 0 0010: DAC signal-processing block PRB_P2 0 0011: DAC signal-processing block PRB_P3 0 0100: DAC signal-processing block PRB_P4 ... 1 1000: DAC signal-processing block PRB_P24 1 1001: DAC signal-processing block PRB_P25 1 1010–1 1111: Reserved. Do not use.

Table 6-74 Page 0 / Register 61 (0x3D)Through Page 0 / Register 62: Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not write.

Table 6-75 Page 0 / Register 63 (0x3F): DAC Data-Path Setup

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Left-channel DAC is powered down. 1: Left-channel DAC is powered up.
D6	R/W	0	0: Right-channel DAC is powered down. 1: Right-channel DAC is powered up.
D5–D4	R/W	01	00: Left-channel DAC data path = off 01: Left-channel DAC data path = left data 10: Left-channel DAC data path = right data 11: Left-channel DAC data path = left-channel and right-channel data [(L + R) / 2]
D3–D2	R/W	01	00: Right-channel DAC data path = off 01: Right-channel DAC data path = right data 10: Right-channel DAC data path = left data 11: Right-channel DAC data path = left-channel and right-channel data [(L + R) / 2]
D1–D0	R/W	00	00: DAC-channel volume-control soft-stepping is enabled for one step per sample period. 01: DAC-channel volume-control soft-stepping is enabled for one step per two sample periods. 10: DAC-channel volume-control soft-stepping is disabled. 11: Reserved. Do not write this sequence to these bits.

Table 6-76 Page 0 / Register 64 (0x40): DAC Volume Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D4	R/W	0000	Reserved. Write only zeros to these bits.
D3	R/W	1	0: Left-channel DAC not muted 1: Left-channel DAC muted
D2	R/W	1	0: Right-channel DAC not muted 1: Right-channel DAC muted
D1–D0	R/W	00	00: Left and right channels have independent volume control.⁽¹⁾ 01: Left-channel volume control Is the programmed value of right-channel volume control. 10: Right-channel volume control is the programmed value of left-channel volume control. 11: Same as 00

(1) When DRC is enabled, left and right channel volume controls are always independent. Program bits D1–D0 to 00.

Table 6-77 Page 0 / Register 65 (0x41): DAC Left Volume Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	Left DAC Channel Digital Volume Control Setting 0111 1111–0011 0001: Reserved. Do not use 0011 0000: Digital volume control = 24 dB 0010 1111: Digital volume control = 23.5 dB 0010 1110: Digital volume control = 23 dB ... 0000 0001: Digital volume control = 0.5 dB 0000 0000: Digital volume control = 0 dB 1111 1111: Digital volume control = –0.5 dB ... 1000 0010: Digital volume control = –63 dB 1000 0001: Digital volume control = –63.5 dB 1000 0000: Reserved.

Table 6-78 Page 0 / Register 66 (0x42): DAC Right Volume Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	Right DAC Channel Digital Volume Control Setting 0111 1111–0011 0001: Reserved. Do not use 0011 0000: Digital volume control = 24 dB 0010 1111: Digital volume control = 23.5 dB 0010 1110: Digital volume control = 23 dB ... 0000 0001: Digital volume control = 0.5 dB 0000 0000: Digital volume control = 0 dB 1111 1111: Digital volume control = –0.5 dB ... 1000 0010: Digital volume control = –63 dB 1000 0001: Digital volume control = –63.5 dB 1000 0000: Reserved.

Table 6-79 Page 0 / Register 67 (0x43): Headset Detection

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Headset detection disabled 1: Headset detection enabled
D6–D5	R	XX	00: No headset detected 01: Headset without microphone is detected 10: Reserved 11: Headset with microphone is detected
D4–D2	R/W	000	Debounce Programming for Glitch Rejection During Headset Detection⁽¹⁾ 000: 16 ms (sampled with 2-ms clock) 001: 32 ms (sampled with 4-ms clock) 010: 64 ms (sampled with 8-ms clock) 011: 128 ms (sampled with 16-ms clock) 100: 256 ms (sampled with 32-ms clock) 101: 512 ms (sampled with 64-ms clock) 110: Reserved 111: Reserved
D1–D0	R/W	00	Debounce programming for glitch rejection during headset button-press detection 00: 0 ms 01: 8 ms (sampled with 1-ms clock) 10: 16 ms (sampled with 2-ms clock) 11: 32 ms (sampled with 4-ms clock)

(1) Note that these times are generated using the 1 MHz reference clock which is defined in Page 3 / Register 16.

Table 6-80 Page 0 / Register 68 (0x44): DRC Control 1

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	Reserved. Write only the reset value to these bits.
D6	R/W	0	0: DRC disabled for left channel 1: DRC enabled for left channel
D5	R/W	0	0: DRC disabled for right channel 1: DRC enabled for right channel
D4–D2	R/W	011	000: DRC threshold = –3 dB 001: DRC threshold = –6 dB 010: DRC threshold = –9 dB 011: DRC threshold = –12 dB 100: DRC threshold = –15 dB 101: DRC threshold = –18 dB 110: DRC threshold = –21 dB 111: DRC threshold = –24 dB
D1–D0	R/W	11	00: DRC hysteresis = 0 dB 01: DRC hysteresis = 1 dB 10: DRC hysteresis = 2 dB 11: DRC hysteresis = 3 dB

Table 6-81 Page 0 / Register 69 (0x45): DRC Control 2

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D	R	0	Reserved. Write only the reset value to these bits.
D6–D3	R/W	0111	DRC Hold Time 0000: DRC Hold Disabled 0001: DRC Hold Time = 32 DAC Word Clocks 0010: DRC Hold Time = 64 DAC Word Clocks 0011: DRC Hold Time = 128 DAC Word Clocks 0100: DRC Hold Time = 256 DAC Word Clocks 0101: DRC Hold Time = 512 DAC Word Clocks 0110: DRC Hold Time = 1024 DAC Word Clocks 0111: DRC Hold Time = 2048 DAC Word Clocks 1000: DRC Hold Time = 4096 DAC Word Clocks 1001: DRC Hold Time = 8192 DAC Word Clocks 1010: DRC Hold Time = 16 384 DAC Word Clocks 1011: DRC Hold Time = 32 768 DAC Word Clocks 1100: DRC Hold Time = 65 536 DAC Word Clocks 1101: DRC Hold Time = 98 304 DAC Word Clocks 1110: DRC Hold Time = 131 072 DAC Word Clocks 1111: DRC Hold Time = 163 840 DAC Word Clocks
D2-D0	R	000	Reserved. Write only the reset value to these bits.

Table 6-82 Page 0 / Register 70 (0x46): DRC Control 3

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
0000: DRC attack rate = 4 dB (AR), or 4 db per sample time (t_S) 0001: DRC attack rate = AR / 2 dB 0010: DRC attack rate = AR / 2² dB 0011: DRC attack rate = AR / 2³ dB 0100: DRC attack rate = AR / 2⁴ dB 0101: DRC attack rate = AR / 2⁵ dB 0110: DRC attack rate = AR / 2⁶ dB 0111: DRC attack rate = AR / 2⁷ dB 1000: DRC attack rate = AR / 2⁸ dB 1001: DRC attack rate = AR / 2⁹ dB 1010: DRC attack rate = AR / 2¹⁰ dB 1011: DRC attack rate = AR / 2¹¹ dB 1100: DRC attack rate = AR / 2¹² dB 1101: DRC attack rate = AR / 2¹³ dB 1110: DRC attack rate = AR / 2¹⁴ dB 1111: DRC attack rate = AR / 2¹⁵ dB
D7–D4	R/W	0000	0000: DRC attack rate = 4 dB per DAC Word Clock 0001: DRC attack rate = 2 dB per DAC word clock 0010: DRC attack rate = 1 dB per DAC word clock ... 1110: DRC attack rate = 2.4414e–5 dB per DAC word clock 1111: DRC attack rate = 1.2207e–5 dB per DAC word clock
D3–D0	R/W	0000	Decay Rate is defined as DR / 2^{[bits D3-D0 value]} dB per DAC Word Clock, where DR = 0.015625 dB 0000: DRC decay rate (DR) = 0.015625 dB per DAC Word Clock 0001: DRC decay rate = DR / 2 dB per DAC Word Clock 0010: DRC decay rate = DR / 2² dB per DAC Word Clock 0011: DRC decay rate = DR / 2³ dB per DAC Word Clock 0100: DRC decay rate = DR / 2⁴ dB per DAC Word Clock 0101: DRC decay rate = DR / 2⁵ dB per DAC Word Clock 0110: DRC decay rate = DR / 2⁶ dB per DAC Word Clock 0111: DRC decay rate = DR / 2⁷ dB per DAC Word Clock 1000: DRC decay rate = DR / 2⁸ dB per DAC Word Clock 1001: DRC decay rate = DR / 2⁹ dB per DAC Word Clock 1010: DRC decay rate = DR / 2¹⁰ dB per DAC Word Clock 1011: DRC decay rate = DR / 2¹¹ dB per DAC Word Clock 1100: DRC decay rate = DR / 2¹² dB per DAC Word Clock 1101: DRC decay rate = DR / 2¹³ dB per DAC Word Clock 1110: DRC decay rate = DR / 2¹⁴ dB per DAC Word Clock 1111: DRC decay rate = DR / 2¹⁵ dB per DAC Word Clock

Table 6-83 Page 0 / Register 71 (0x47): Left Beep Generator ⁽¹⁾

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Beep generator is disabled. 1: Beep generator is enabled (self-clearing based on beep duration).
D6	R/W	0	Reserved. Write only reset value.
D5–D0	R/W	00 0000	00 0000: Left-channel beep volume control = 2 dB 00 0001: Left-channel beep volume control = 1 dB 00 0010: Left-channel beep volume control = 0 dB 00 0011: Left-channel beep volume control = –1 dB ... 11 1110: Left-channel beep volume control = –60 dB 11 1111: Left-channel beep volume control = –61 dB

(1) The beep generator is only available in PRB_P25 DAC processing mode.

Table 6-84 Page 0 / Register 72 (0x48): Right Beep Generator

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D6	R/W	00	00: Left and right channels have independent beep volume control. 01: Left-channel beep volume control is the programmed value of right-channel beep volume control. 10: Right-channel beep volume control is the programmed value of left-channel beep volume control. 11: Same as 00
D5–D0	R/W	00 0000	00 0000: Right-channel beep volume control = 2 dB 00 0001: Right-channel beep volume control = 1 dB 00 0010: Right-channel beep volume control = 0 dB 00 0011: Right-channel beep volume control = –1 dB ... 11 1110: Right-channel beep volume control = –60 dB 11 1111: Right-channel beep volume control = –61 dB

Table 6-85 Page 0 / Register 73 (0x49): Beep Length MSB

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	8 MSBs out of 24 bits for the number of samples for which the beep must be generated.

Table 6-86 Page 0 / Register 74 (0x4A): Beep-Length Middle Bits

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	8 middle bits out of 24 bits for the number of samples for which the beep must be generated.

Table 6-87 Page 0 / Register 75 (0x4B): Beep Length LSB

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	1110 1110	8 LSBs out of 24 bits for the number of samples for which beep must be generated.

Table 6-88 Page 0 / Register 76 (0x4C): Beep Sin(x) MSB

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0001 0000	8 MSBs out of 16 bits for sin(2π × f_in / f_S), where f_in is the beep frequency and f_S is the DAC sample rate.

Table 6-89 Page 0 / Register 77 (0x4D): Beep Sin(x) LSB

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	1101 1000	8 LSBs out of 16 bits for sin(2π × f_in / f_S), where f_in is the beep frequency and f_S is the DAC sample rate.

Table 6-90 Page 0 / Register 78 (0x4E): Beep Cos(x) MSB

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0111 1110	8 MSBs out of 16 bits for cos(2π × f_in / f_S), where f_in is the beep frequency and f_S is the DAC sample rate.

Table 6-91 Page 0 / Register 79 (0x4F): Beep Cos(x) LSB

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	1110 0011	8 LSBs out of 16 bits for cos(2π × f_in / f_S), where f_in is the beep frequency and f_S is the DAC sample rate.

Table 6-92 Page 0 / Register 80 (0x50) Through Page 0 / Register 115 (0x73): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not use.

Table 6-93 Page 0 / Register 116 (0x74): VOL/MICDET-Pin SAR ADC — Volume Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: DAC volume control is controlled by control register. (7-bit Vol ADC is powered down) 1: DAC volume control is controlled by pin.
D6	R/W	0	0: Internal on-chip RC oscillator is used for the 7-bit Vol ADC for pin volume control. 1: MCLK is used for the 7-bit Vol ADC for pin volume control.
D5–D4	R/W	00	00: No hysteresis for volume control ADC output 01: Hysteresis of ±1 bit 10: Hysteresis of ±2 bits 11: Reserved. Do not write this sequence to these bits.
D3	R/W	0	Reserved. Write only reset value.
D2–D0	R/W	000	Throughput of the 7-bit Vol ADC for pin volume control, frequency based on MCLK or internal oscillator.
				MCLK = 12 MHz	Internal Oscillator Source
			000: Throughput = 001: Throughput = 010: Throughput = 011: Throughput = 100: Throughput = 101: Throughput = 110: Throughput = 111: Throughput =	15.625 Hz 31.25 Hz 62.5 Hz 125 Hz 250 Hz 500 Hz 1 kHz 2 kHz	10.68 Hz 21.35 Hz 42.71 Hz 8.2 Hz 170 Hz 340 Hz 680 Hz 1.37 kHz Note: These values are based on a nominal oscillator frequency of 8.2 MHz. The values scale to the actual oscillator frequency.

Table 6-94 Page 0 / Register 117 (0x75): VOL/MICDET-Pin Gain

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	Reserved. Write only zero to this bit.
D6–D0	R	XXX XXXX	000 0000: Gain applied by pin volume control = 18 dB 000 0001: Gain applied by pin volume control = 17.5 dB 000 0010: Gain applied by pin volume control = 17 dB ... 010 0011: Gain applied by pin volume control = 0.5 dB 010 0100: Gain applied by pin volume control = 0 dB 010 0101: Gain applied by pin volume control = –0.5 dB ... 101 1001: Gain applied by pin volume control = –26.5 dB 101 1010: Gain applied by pin volume control = –27 dB 101 1011: Gain applied by pin volume control = –28 dB ... 111 1101: Gain applied by pin volume control = –62 dB 111 1110: Gain applied by pin volume control = –63 dB 111 1111: Reserved.

Table 6-95 Page 0 / Register 118 (0x76) Through Page 0 / Register 127 (0x7F): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	XXXX XXXX	Reserved. Do not use.

6.4.2.2 Control Registers, Page 1: DAC, Power-Controls, and MISC Logic-Related Programmability

Table 6-96 Page 1 / Register 0 (0x00): Page Control Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	0000 0000: Page 0 selected 0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected

Table 6-97 Page 1 / Register 1 (0x01) Through Page 1 / Register 29 (0x1D): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	XXXX XXXX	Reserved. Do not use.

Table 6-98 Page 1 / Register 30 (0x1E): Headphone and Speaker Amplifier Error Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D2	R/W	0000 00	Reserved
D1	R/W	0	0: Reset SPK power-up control bits on short-circuit detection. 1: SPK power-up control bits remain unchanged on short-circuit detection.
D0	R/W	0	0: Reset HPL and HPR power-up control bits on short-circuit detection if page 1 / register 31, D1 = 1. 1: HPL and HPR power-up control bits remain unchanged on short-circuit detection.

Table 6-99 Page 1 / Register 31 (0x1F): Headphone Drivers

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: HPL output driver is powered down. 1: HPL output driver is powered up.
D6	R/W	0	0: HPR output driver is powered down. 1: HPR output driver is powered up.
D5	R/W	0	Reserved. Write only zero to this bit.
D4–D3	R/W	0	00: Output common-mode voltage = 1.35 V 01: Output common-mode voltage = 1.5 V 10: Output common-mode voltage = 1.65 V 11: Output common-mode voltage = 1.8 V
D2	R/W	1	Reserved. Write only 1 to this bit.
D1	R/W	0	0: If short-circuit protection is enabled for headphone driver and short circuit detected, device limits the maximum current to the load. 1: If short-circuit protection is enabled for headphone driver and short circuit detected, device powers down the output driver.
D0	R	0	0: Short circuit is not detected on the headphone driver. 1: Short circuit is detected on the headphone driver.

Table 6-100 Page 1 / Register 32 (0x20): Class-D Speaker Amplifier

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Class-D output driver is powered down. 1: Class-D output driver is powered up.
D6–D1	R/W	000 011	Reserved. Write only the reset value to this bit.
D0	R	0	0: Short circuit is not detected on the class-D driver. Valid only if class-D amplifier is powered up. For short-circuit flag sticky bit, see page 0 / register 44. 1: Short circuit is detected on the class-D driver. Valid only if class-D amp is powered-up. For short- circuit flag sticky bit, see page 0 / register 44.

Table 6-101 Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: If the power down sequence is activated by device software, power down using page 1 / register 46, ││ bit D7, then power down the DAC simultaneously with the HP and SP amplifiers. 1: If the power down sequence is activated by device software, power down using page 1 / register 46, ││ bit D7, then power down DAC only after HP and SP amplifiers are completely powered down. This is to ││ optimize power-down POP.
D6–D3	R/W	0111	0000: Driver power-on time = 0 μs 0001: Driver power-on time = 15.3 μs 0010: Driver power-on time = 153 μs 0011: Driver power-on time = 1.53 ms 0100: Driver power-on time = 15.3 ms 0101: Driver power-on time = 76.2 ms 0110: Driver power-on time = 153 ms 0111: Driver power-on time = 304 ms 1000: Driver power-on time = 610 ms 1001: Driver power-on time = 1.22 s 1010: Driver power-on time = 3.04 s 1011: Driver power-on time = 6.1 s 1100–1111: Reserved. Do not write these sequences to these bits. Note: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual oscillator frequency.
D2–D1	R/W	11	00: Driver ramp-up step time = 0 ms 01: Driver ramp-up step time = 0.98 ms 10: Driver ramp-up step time = 1.95 ms 11: Driver ramp-up step time = 3.9 ms Note: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual oscillator frequency.
D0	R/W	0	0: Weakly driven output common-mode voltage is generated from resistor divider of the AVDD supply. 1: Reserved

Table 6-102 Page 1 / Register 34 (0x22): Output Driver PGA Ramp-Down Period Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	Reserved. Write only the reset value to this bit.
D6–D4	R/W	000	Speaker power-up wait time (duration based on using internal oscillator) 000: Wait time = 0 ms 001: Wait time = 3.04 ms 010: Wait time = 7.62 ms 011: Wait time = 12.2 ms 100: Wait time = 15.3 ms 101: Wait time = 19.8 ms 110: Wait time = 24.4 ms 111: Wait time = 30.5 ms Note: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual oscillator frequency.
D3–D0	R/W	0000	Reserved. Write only the reset value to these bits.

Table 6-103 Page 1 / Register 35 (0x23): DAC_L and DAC_R Output Mixer Routing

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D6	R/W	00	00: DAC_L is not routed anywhere. 01: DAC_L is routed to the left-channel mixer amplifier. 10: DAC_L is routed directly to the HPL driver. 11: Reserved
D5	R/W	0	0: AIN1 input is not routed to the left-channel mixer amplifier. 1: AIN1 input is routed to the left-channel mixer amplifier.
D4		0	0: AIN2 input is not routed to the left-channel mixer amplifier. 1: AIN2 input is routed to the left-channel mixer amplifier.
D3–D2	R/W	00	00: DAC_R is not routed anywhere. 01: DAC_R is routed to the right-channel mixer amplifier. 10: DAC_R is routed directly to the HPR driver. 11: Reserved
D1	R/W	0	0: AIN2 input is not routed to the right-channel mixer amplifier. 1: AIN2 input is routed to the right-channel mixer amplifier.
D0	R/W	0	0: HPL driver output is not routed to the HPR driver. 1: HPL driver output is routed to the HPR driver input (used for differential output mode).

Table 6-104 Page 1 / Register 36 (0x24): Left Analog Volume to HPL

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Left-channel analog volume control is not routed to HPL output driver. 1: Left-channel analog volume control is routed to HPL output driver.
D6–D0	R/W	111 1111	Left-channel analog volume control gain (non-linear) for the HPL output driver, 0 dB to –78 dB. See Table 6-24.

Table 6-105 Page 1 / Register 37 (0x25): Right Analog Volume to HPR

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Right-channel analog volume control is not routed to HPR output driver. 1: Right-channel analog volume control is routed to HPR output driver.
D6–D0	R/W	111 1111	Right-channel analog volume control gain (non-linear) for the HPR output driver, 0 dB to –78 dB. See Table 6-24.

Table 6-106 Page 1 / Register 38 (0x26): Left Analog Volume to SPK

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Left-channel analog volume control output is not routed to class-D output driver. 1: Left-channel analog volume control output is routed to class-D output driver.
D6–D0	R/W	111 1111	Left-channel analog volume control output gain (non-linear) for the class-D output driver, 0 dB to –78 dB. See Table 6-24.

Table 6-107 Page 1 / Register 39 (0x27): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R	0111 1111	Reserved Do not use.

Table 6-108 Page 1 / Register 40 (0x28): HPL Driver

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	Reserved. Write only zero to this bit.
D6–D3	R/W	0000	0000: HPL driver PGA = 0 dB 0001: HPL driver PGA = 1 dB 0010: HPL driver PGA = 2 dB ... 1000: HPL driver PGA = 8 dB 1001: HPL driver PGA = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits.
D2	R/W	0	0: HPL driver is muted. 1: HPL driver is not muted.
D1	R/W	1	Reserved
D0	R	0	0: Not all programmed gains to HPL have been applied yet. 1: All programmed gains to HPL have been applied.

Table 6-109 Page 1 / Register 41 (0x29): HPR Driver

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	Reserved. Write only zero to this bit.
D6–D3	R/W	0000	0000: HPR driver PGA = 0 dB 0001: HPR driver PGA = 1 dB 0010: HPR driver PGA = 2 dB ... 1000: HPR driver PGA = 8 dB 1001: HPR driver PGA = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits.
D2	R/W	0	0: HPR driver is muted. 1: HPR driver is not muted.
D1	R/W	1	Reserved. Write only '1' to this bit.
D0	R	0	0: Not all programmed gains to HPR have been applied yet. 1: All programmed gains to HPR have been applied.

Table 6-110 Page 1 / Register 42 (0x2A): Class-D Speaker (SPK) Driver

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D5	R/W	000	Reserved. Write only zeros to these bits.
D4–D3	R/W	00	00: Class-D driver output stage gain = 6 dB 01: Class-D driver output stage gain = 12 dB 10: Class-D driver output stage gain = 18 dB 11: Class-D driver output stage gain = 24 dB
D2	R/W	0	0: Class-D driver is muted. 1: Class-D driver is not muted.
D1	R/W	0	Reserved. Write only zero to this bit.
D0	R	0	0: Not all programmed gains to the Class-D driver have been applied yet. 1: All programmed gains to the Class-D driver have been applied.

Table 6-111 Page 1 / Register 43 (0x2B): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7-D0	R	0000 0000	Reserved. Do not use.

Table 6-112 Page 1 / Register 44 (0x2C): HP Driver Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D5	R/W	000	Debounce time for the headset short-circuit detection
			⁽¹⁾	MCLK/DIV (Page 3 / register 16) = 1-MHz Source	Internal Oscillator Source
			000: Debounce time = 001: Debounce time = 010: Debounce time = 011: Debounce time = 100: Debounce time = 101: Debounce time = 110: Debounce time = 111: Debounce time =	0 μs 8 μs 16 μs 32 μs 64 μs 128 μs 256 μs 512 μs	0 μs 7.8 μs 15.6 μs 31.2 μs 62.4 μs 124.9 μs 250 μs 500 μs Note: These values are based on a nominal oscillator frequency of 8.2 MHz. The values scale to the actual oscillator frequency.
D4–D3	R/W	00	00: Default mode for the DAC 01: DAC performance increased by increasing the current 10: Reserved 11: DAC performance increased further by increasing the current again
D2	R/W	0	0: HPL output driver is programmed as headphone driver. 1: HPL output driver is programmed as lineout driver.
D1	R/W	0	0: HPR output driver is programmed as headphone driver. 1: HPR output driver is programmed as lineout driver.
D0	R/W	0	Reserved. Write only zero to this bit.

(1) The clock used for the debounce has a clock period = debounce duration / 8.

Table 6-113 Page 1 / Register 45 (0x2D): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	XXXX XXXX	Reserved. Do not write to these registers.

Table 6-114 Page 1 / Register 46 (0x2E): MICBIAS

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: Device software power down is not enabled. 1: Device software power down is enabled.
D6–D4	R/W	000	Reserved. Write only zeros to these bits.
D3	R/W	0	0: Programmed MICBIAS is not powered up if headset detection is enabled but headset is not inserted. 1: Programmed MICBIAS is powered up even if headset is not inserted.
D2	R/W	0	Reserved. Write only zero to this bit.
D1–D0	R/W	00	00: MICBIAS output is powered down. 01: MICBIAS output is powered to 2 V. 10: MICBIAS output is powered to 2.5 V. 11: MICBIAS output is powered to AVDD.

Table 6-115 Page 1 / Register 50 (0x32): Input CM Settings

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	0	0: AIN1 input is floating, if it is not used for the analog bypass. 1: AIN1 input is connected to CM internally, if it is not used for the analog bypass.
D6	R/W	0	0: AIN2 input is floating, if it is not used for the analog bypass. 1: AIN2 input is connected to CM internally, if it is not used for the analog bypass.
D5–D0	R/W	00 0000	Reserved. Write only zeros to these bits.

Table 6-116 Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	XXXX XXXX	Reserved. Write only the reset value to these bits.

6.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer

Default values shown for this page only become valid 100 μs following a hardware or software reset.

Table 6-117 Page 3 / Register 0 (0x00): Page Control Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	0000 0000: Page 0 selected 0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected

The only register used in page 3 is register 16. The remaining page-3 registers are reserved and must not be written to.

Table 6-118 Page 3 / Register 16 (0x10): Timer Clock MCLK Divider

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7	R/W	1	0: Internal oscillator is used for programmable delay timer. 1: External MCLK⁽¹⁾ is used for programmable delay timer.
D6–D0	R/W	000 0001	MCLK Divider to Generate 1-MHz Clock for the Programmable Delay Timer 000 0000: MCLK divider = 128 000 0001: MCLK divider = 1 000 0010: MCLK divider = 2 ... 111 1110: MCLK divider = 126 111 1111: MCLK divider = 127

(1) External clock is used only to control the delay programmed between the conversions and not used for doing the actual conversion. This feature is provided in case a more accurate delay is desired because the internal oscillator frequency varies from device to device.

6.4.2.4 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)

Default values shown for this page only become valid 100 μs following a hardware or software reset.

Table 6-119 Page 8 / Register 0 (0x00): Page Control Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	0000 0000: Page 0 selected 0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected

The remaining page-8 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3100. Reserved registers must not be written to.

The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32 768 to 32 767. When programming any coefficient value for a filter, the MSB register must always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers must be written in this sequence. is a list of the page-8 registers, excepting the previously described register 0.

Table 6-120 Page 8 / Register 1 (0x01): DAC Coefficient RAM Control

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D3	R/W	0000 0	Reserved. Write only the reset value.
D2	R/W	0	DAC Adaptive Filtering Control 0: Adaptive filtering disabled in DAC processing block 1: Adaptive filtering enabled in DAC processing block
D1	R	0	DAC Adaptive Filter Buffer Control Flag 0: In adaptive filter mode, DAC processing block accesses DAC coefficient Buffer A and the external control interface accesses DAC coefficient Buffer B 1: In adaptive filter mode, DAC processing block accesses DAC coefficient Buffer B and the external control interface accesses DAC coefficient Buffer A
D0	R/W	0	DAC Adaptive Filter Buffer Switch Control 0: DAC coefficient buffers are not switched at the next frame boundary. 1: DAC coefficient buffers are switched at the next frame boundary, if adaptive filtering mode is enabled. This bit self-clears on switching.

Table 6-121 Page-8 DAC Buffer A Registers

REGISTER NUMBER	RESET VALUE	REGISTER NAME
2 (0x02)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad A
3 (0x03)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad A
4 (0x04)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad A
5 (0x05)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad A
6 (0x06)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad A
7 (0x07)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad A
8 (0x08)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad A
9 (0x09)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad A
10 (0x0A)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad A
11 (0x0B)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad A
12 (0x0C)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad B
13 (0x0D)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad B
14 (0x0E)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad B
15 (0x0F)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad B
16 (0x10)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad B
17 (0x11)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad B
18 (0x12)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad B
19 (0x13)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad B
20 (0x14)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad B
21 (0x15)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad B
22 (0x16)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad C
23 (0x17)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad C
24 (0x18)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad C
25 (0x19)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad C
26 (0x1A)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad C
27 (0x1B)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad C
28 (0x1C)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad C
29 (0x1D)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad C
30 (0x1E)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad C
31 (0x1F)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad C
32 (0x20)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad D
33 (0x21)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad D
34 (0x22)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad D
35 (0x23)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad D
36 (0x24)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad D
37 (0x25)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad D
38 (0x26)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad D
39 (0x27)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad D
40 (0x28)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad D
41 (0x29)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad D
42 (0x2A)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad E
43 (0x2B)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad E
44 (0x2C)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad E
45 (0x2D)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad E
46 (0x2E)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad E
47 (0x2F)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad E
48 (0x30)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad E
49 (0x31)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad E
50 (0x32)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad E
51 (0x33)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad E
52 (0x34)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad F
53 (0x35)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad F
54 (0x36)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad F
55 (0x37)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad F
56 (0x38)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad F
57 (0x39)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad F
58 (0x3A)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad F
59 (0x3B)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad F
60 (0x3C)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad F
61 (0x3D)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad F
62 (0x3E)	0000 0000	Reserved
63 (0x3F)	0000 0000	Reserved
64 (0x40)	0000 0000	8 MSBs of 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25
65 (0x41)	0000 0000	8 LSBs of 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25
66 (0x42)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad A
67 (0x43)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad A
68 (0x44)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad A
69 (0x45)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad A
70 (0x46)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad A
71 (0x47)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad A
72 (0x48)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad A
73 (0x49)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad A
74 (0x4A)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad A
75 (0x4B)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad A
76 (0x4C)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad B
77 (0x4D)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad B
78 (0x4E)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad B
79 (0x4F)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad B
80 (0x50)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad B
81 (0x51)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad B
82 (0x52)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad B
83 (0x53)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad B
84 (0x54)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad B
85 (0x55)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad B
86 (0x56)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad C
87 (0x57)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad C
88 (0x58)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad C
89 (0x59)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad C
90 (0x5A)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad C
91 (0x5B)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad C
92 (0x5C)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad C
93 (0x5D)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad C
94 (0x5E)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad C
95 (0x5F)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad C
96 (0x60)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad D
97 (0x61)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad D
98 (0x62)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad D
99 (0x63)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad D
100 (0x64)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad D
101 (0x65)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad D
102 (0x66)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad D
103 (0x67)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad D
104 (0x68)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad D
105 (0x69)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad D
106 (0x6A)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad E
107 (0x6B)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad E
108 (0x6C)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad E
109 (0x6D)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad E
110 (0x6E)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad E
111 (0x6F)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad E
112 (0x70)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad E
113 (0x71)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad E
114 (0x72)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad E
115 (0x73)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad E
116 (0x74)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad F
117 (0x75)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad F
118 (0x76)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad F
119 (0x77)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad F
120 (0x78)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad F
121 (0x79)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad F
122 (0x7A)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad F
123 (0x7B)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad F
124 (0x7C)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad F
125 (0x7D)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad F
126–127	0000 0000	Reserved

6.4.2.5 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)

Default values shown for this page only become valid 100 μs following a hardware or software reset.

Table 6-122 Page 9 / Register 0 (0x00): Page Control Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	0000 0000: Page 0 selected 0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected

The remaining page-9 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3100. Reserved registers must not be written to.

The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32 768 to 32 767. When programming any coefficient value for a filter, the MSB register must always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers must be written in this sequence. is a list of the page-9 registers, excepting the previously described register 0.

Table 6-123 Page-9 DAC Buffer A Registers

REGISTER NUMBER	RESET VALUE	REGISTER NAME
1 (0x01)	XXXX XXXX	Reserved. Do not write to this register.
2 (0x02)	0111 1111	Coefficient N0(15:8) for left DAC-programmable first-order IIR
3 (0x03)	1111 1111	Coefficient N0(7:0) for left DAC-programmable first-order IIR
4 (0x04)	0000 0000	Coefficient N1(15:8) for left DAC-programmable first-order IIR
5 (0x05)	0000 0000	Coefficient N1(7:0) for left DAC-programmable first-order IIR
6 (0x06)	0000 0000	Coefficient D1(15:8) for left DAC-programmable first-order IIR
7 (0x07)	0000 0000	Coefficient D1(7:0) for left DAC-programmable first-order IIR
8 (0x08)	0111 1111	Coefficient N0(15:8) for right DAC-programmable first-order IIR
9 (0x09)	1111 1111	Coefficient N0(7:0) for right DAC-programmable first-order IIR
10 (0x0A)	0000 0000	Coefficient N1(15:8) for right DAC-programmable first-order IIR
11 (0x0B)	0000 0000	Coefficient N1(7:0) for right DAC-programmable first-order IIR
12 (0x0C)	0000 0000	Coefficient D1(15:8) for right DAC-programmable first-order IIR
13 (0x0D)	0000 0000	Coefficient D1(7:0) for right DAC-programmable first-order IIR
14 (0x0E)	0111 1111	Coefficient N0(15:8) for DRC first-order high-pass filter
15 (0x0F)	1111 0111	Coefficient N0(7:0) for DRC first-order high-pass filter
16 (0x10)	1000 0000	Coefficient N1(15:8) for DRC first-order high-pass filter
17 (0x11)	0000 1001	Coefficient N1(7:0) for DRC first-order high-pass filter
18 (0x12)	0111 1111	Coefficient D1(15:8) for DRC first-order high-pass filter
19 (0x13)	1110 1111	Coefficient D1(7:0) for DRC first-order high-pass filter
20 (0x14)	0000 0000	Coefficient N0(15:8) for DRC first-order low-pass filter
21 (0x15)	0001 0001	Coefficient N0(7:0) for DRC first-order low-pass filter
22 (0x16)	0000 0000	Coefficient N1(15:8) for DRC first-order low-pass filter
23 (0x17)	0001 0001	Coefficient N1(7:0) for DRC first-order low-pass filter
24 (0x18)	0111 1111	Coefficient D1(15:8) for DRC first-order low-pass filter
25 (0x19)	1101 1110	Coefficient D1(7:0) for DRC first-order low-pass filter
26–127	0000 0000	Reserved

6.4.2.6 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)

Table 6-1 Page 12 / Register 0 (0x00): Page Control Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	0000 0000: Page 0 selected 0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected

The remaining page-12 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3100. Reserved registers should not be written to.

The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32 768 to 32 767. When programming any coefficient value for a filter, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers should be written in this sequence. is a list of the page-12 registers, excepting the previously described register 0.

Table 6-124 Page-12 AC Buffer B Registers

REGISTER NUMBER	RESET VALUE	REGISTER NAME
1 (0x01)	0000 0000	Reserved. Do not write to this register.
2 (0x02)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad A
3 (0x03)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad A
4 (0x04)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad A
5 (0x05)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad A
6 (0x06)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad A
7 (0x07)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad A
8 (0x08)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad A
9 (0x09)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad A
10 (0x0A)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad A
11 (0x0B)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad A
12 (0x0C)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad B
13 (0x0D)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad B
14 (0x0E)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad B
15 (0x0F)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad B
16 (0x10)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad B
17 (0x11)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad B
18 (0x12)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad B
19 (0x13)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad B
20 (0x14)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad B
21 (0x15)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad B
22 (0x16)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad C
23 (0x17)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad C
24 (0x18)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad C
25 (0x19)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad C
26 (0x1A)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad C
27 (0x1B)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad C
28 (0x1C)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad C
29 (0x1D)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad C
30 (0x1E)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad C
31 (0x1F)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad C
32 (0x20)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad D
33 (0x21)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad D
34 (0x22)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad D
35 (0x23)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad D
36 (0x24)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad D
37 (0x25)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad D
38 (0x26)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad D
39 (0x27)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad D
40 (0x28)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad D
41 (0x29)	0000 0000	Coefficient D2(17:0) for left DAC-programmable biquad D
42 (0x2A)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad E
43 (0x2B)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad E
44 (0x2C)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad E
45 (0x2D)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad E
46 (0x2E)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad E
47 (0x2F)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad E
48 (0x30)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad E
49 (0x31)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad E
50 (0x32)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad E
51 (0x33)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad E
52 (0x34)	0111 1111	Coefficient N0(15:8) for left DAC-programmable biquad F
53 (0x35)	1111 1111	Coefficient N0(7:0) for left DAC-programmable biquad F
54 (0x36)	0000 0000	Coefficient N1(15:8) for left DAC-programmable biquad F
55 (0x37)	0000 0000	Coefficient N1(7:0) for left DAC-programmable biquad F
56 (0x38)	0000 0000	Coefficient N2(15:8) for left DAC-programmable biquad F
57 (0x39)	0000 0000	Coefficient N2(7:0) for left DAC-programmable biquad F
58 (0x3A)	0000 0000	Coefficient D1(15:8) for left DAC-programmable biquad F
59 (0x3B)	0000 0000	Coefficient D1(7:0) for left DAC-programmable biquad F
60 (0x3C)	0000 0000	Coefficient D2(15:8) for left DAC-programmable biquad F
61 (0x3D)	0000 0000	Coefficient D2(7:0) for left DAC-programmable biquad F
62 (0x3E)	0000 0000	Reserved
63 (0x3F)	0000 0000	Reserved
64 (0x40)	0000 0000	8 MSBs 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25
65 (0x41)	0000 0000	8 LSBs 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25
66 (0x42)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad A
67 (0x43)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad A
68 (0x44)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad A
69 (0x45)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad A
70 (0x46)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad A
71 (0x47)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad A
72 (0x48)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad A
73 (0x49)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad A
74 (0x4A)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad A
75 (0x4B)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad A
76 (0x4C)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad B
77 (0x4D)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad B
78 (0x4E)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad B
79 (0x4F)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad B
80 (0x50)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad B
81 (0x51)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad B
82 (0x52)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad B
83 (0x53)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad B
84 (0x54)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad B
85 (0x55)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad B
86 (0x56)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad C
87 (0x57)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad C
88 (0x58)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad C
89 (0x59)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad C
90 (0x5A)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad C
91 (0x5B)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad C
92 (0x5C)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad C
93 (0x5D)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad C
94 (0x5E)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad C
95 (0x5F)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad C
96 (0x60)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad D
97 (0x61)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad D
98 (0x62)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad D
99 (0x63)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad D
100 (0x64)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad D
101 (0x65)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad D
102 (0x66)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad D
103 (0x67)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad D
104 (0x68)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad D
105 (0x69)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad D
106 (0x6A)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad E
107 (0x6B)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad E
108 (0x6C)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad E
109 (0x6D)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad E
110 (0x6E)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad E
111 (0x6F)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad E
112 (0x70)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad E
113 (0x71)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad E
114 (0x72)	0000 0000	Coefficient ND2(15:8) for right DAC-programmable biquad E
115 (0x73)	0000 0000	Coefficient ND2(7:0) for right DAC-programmable biquad E
116 (0x74)	0111 1111	Coefficient N0(15:8) for right DAC-programmable biquad F
117 (0x75)	1111 1111	Coefficient N0(7:0) for right DAC-programmable biquad F
118 (0x76)	0000 0000	Coefficient N1(15:8) for right DAC-programmable biquad F
119 (0x77)	0000 0000	Coefficient N1(7:0) for right DAC-programmable biquad F
120 (0x78)	0000 0000	Coefficient N2(15:8) for right DAC-programmable biquad F
121 (0x79)	0000 0000	Coefficient N2(7:0) for right DAC-programmable biquad F
122 (0x7A)	0000 0000	Coefficient D1(15:8) for right DAC-programmable biquad F
123 (0x7B)	0000 0000	Coefficient D1(7:0) for right DAC-programmable biquad F
124 (0x7C)	0000 0000	Coefficient D2(15:8) for right DAC-programmable biquad F
125 (0x7D)	0000 0000	Coefficient D2(7:0) for right DAC-programmable biquad F
126–127	0000 0000	Reserved

6.4.2.7 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)

Table 6-2 Page 13 / Register 0 (0x00): Page Control Register

BIT	READ/ WRITE	RESET VALUE	DESCRIPTION
D7–D0	R/W	0000 0000	0000 0000: Page 0 selected 0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected

The remaining page-13 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3100. Reserved registers must not be written to.

The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32 768 to 32 767. When programming any coefficient value for a filter, the MSB register must always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers must be written in this sequence. is a list of the page-13 registers, excepting the previously described register 0.

Table 6-125 Page-13 DAC Buffer B Registers

REGISTER NUMBER	RESET VALUE	REGISTER NAME
1	0000 0000	Reserved. Do not write to this register.
2 (0x02)	0111 1111	Coefficient N0(15:8) for left DAC-programmable first-order IIR
3 (0x03)	1111 1111	Coefficient N0(7:0) for left DAC-programmable first-order IIR
4 (0x04)	0000 0000	Coefficient N1(15:8) for left DAC-programmable first-order IIR
5 (0x05)	0000 0000	Coefficient N1(7:0) for left DAC-programmable first-order IIR
6 (0x06)	0000 0000	Coefficient D1(15:8) for left DAC-programmable first-order IIR
7 (0x07)	0000 0000	Coefficient D1(7:0) for left DAC-programmable first-order IIR
8 (0x08)	0111 1111	Coefficient N0(15:8) for right DAC-programmable first-order IIR
9 (0x09)	1111 1111	Coefficient N0(7:0) for right DAC-programmable first-order IIR
10 (0x0A)	0000 0000	Coefficient N1(15:8) for right DAC-programmable first-order IIR
11 (0x0B)	0000 0000	Coefficient N1(7:0) for right DAC-programmable first-order IIR
12 (0x0C)	0000 0000	Coefficient D1(15:8) for right DAC-programmable first-order IIR
13 (0x0D)	0000 0000	Coefficient D1(7:0) for right DAC-programmable first-order IIR
14 (0x0E)	0111 1111	Coefficient N0(15:8) for DRC first-order high-pass filter
15 (0x0F)	1111 0111	Coefficient N0(7:0) for DRC first-order high-pass filter
16 (0x10)	1000 0000	Coefficient N1(15:8) for DRC first-order high-pass filter
17 (0x11)	0000 1001	Coefficient N1(7:0) for DRC first-order high-pass filter
18 (0x12)	0111 1111	Coefficient D1(15:8) for DRC first-order high-pass filter
19 (0x13)	1110 1111	Coefficient D1(7:0) for DRC first-order high-pass filter
20 (0x14)	0000 0000	Coefficient N0(15:8) for DRC first-order low-pass filter
21 (0x15)	0001 0001	Coefficient N0(7:0) for DRC first-order low-pass filter
22 (0x16)	0000 0000	Coefficient N1(15:8) for DRC first-order low-pass filter
23 (0x17)	0001 0001	Coefficient N1(7:0) for DRC first-order low-pass filter
24 (0x18)	0111 1111	Coefficient D1(15:8) for DRC first-order low-pass filter
25 (0x19)	1101 1110	Coefficient D1(7:0) for DRC first-order low-pass filter
26–127	0000 0000	Reserved

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Detailed Description

6.1 Overview

6.2 Functional Block Diagram

6.3 Feature Description

6.3.1 Power-Supply Sequence

6.3.2 Reset

6.3.3 Device Start-Up Lockout Times

6.3.4 PLL Start-Up

6.3.5 Power-Stage Reset

6.3.6 Software Power Down

6.3.7 Audio Analog I/O

6.3.8 Digital Processing Low-Power Modes

6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

Table 6-1 PRB_P7 Alternative Processing Blocks, 24.28 mW

Table 6-2 PRB_P7 Alternative Processing Blocks, 24.5 mW

6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

Table 6-3 PRB_P12 Alternative Processing Blocks, 15.4 mW

Table 6-4 PRB_P12 Alternative Processing Blocks, 15.54 mW

6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

Table 6-5 PRB_P7 Alternative Processing Blocks, 22.44 mW

Table 6-6 PRB_P7 Alternative Processing Blocks, 22.83 mW

6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

Table 6-7 PRB_P12 Alternative Processing Blocks, 14.49 mW

Table 6-8 PRB_P12 Alternative Processing Blocks, 14.42 mW

6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

Table 6-9 PRB_P17 Alternative Processing Blocks, 27.05 mW

6.3.8.6 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V

6.3.9 Analog Signals

6.3.9.1 MICBIAS

Table 6-10 MICBIAS Settings

6.3.9.2 Analog Inputs AIN1 and AIN2

6.3.10 Audio DAC and Audio Analog Outputs

6.3.10.1 DAC

6.3.10.1.1 DAC Processing Blocks

Table 6-11 Overview – DAC Predefined Processing Blocks

6.3.10.1.2 DAC Processing Blocks — Details

6.3.10.1.2.1 Three Biquads, Filter A

6.3.10.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B

6.3.10.1.2.3 Six Biquads, First-Order IIR, Filter A or B

6.3.10.1.2.4 IIR, Filter B or C

6.3.10.1.2.5 Four Biquads, DRC, Filter B

6.3.10.1.2.6 Four Biquads, Filter B

6.3.10.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C

6.3.10.1.2.8 Four Biquads, First-Order IIR, Filter C

6.3.10.1.2.9 Two Biquads, 3D, Filter A

6.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A

6.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A

6.3.10.1.3 DAC User-Programmable Filters

Table 6-12 Adaptive-Mode Filter-Coefficient Buffer Switching

6.3.10.1.3.1 First-Order IIR Section

Table 6-13 DAC IIR Filter Coefficients

6.3.10.1.3.2 Biquad Section

Table 6-14 DAC Biquad Filter Coefficients

6.3.10.1.4 DAC Interpolation Filter Characteristics

6.3.10.1.4.1 Interpolation Filter A

Table 6-15 Specification for DAC Interpolation Filter A

6.3.10.1.4.2 Interpolation Filter B

Table 6-16 Specification for DAC Interpolation Filter B

6.3.10.1.4.3 Interpolation Filter C

Table 6-17 Specification for DAC Interpolation Filter C

6.3.10.2 DAC Digital-Volume Control

6.3.10.3 Volume Control Pin

Table 6-18 VOL/MICDET Pin Gain Mapping

Table 6-19 VOL/MICDET Pin Gain Scaling

6.3.10.4 Dynamic Range Compression

Table 6-20 The DRC HPF and LPF Coefficients

6.3.10.4.1 DRC Threshold

6.3.10.4.2 DRC Hysteresis

6.3.10.4.3 DRC Hold Time

6.3.10.4.4 DRC Attack Rate

6.3.10.4.5 DRC Decay Rate

6.3.10.4.6 Example Setup for DRC

6.3.10.5 Headphone Detection

Table 6-21 Headphone Detection Block Registers

6.3.10.6 Interrupts

6.3.10.7 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)

6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

6.3.8.6 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V,
HPVDD = 3 V

Table 6-24 Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1)⁽¹⁾

6.3.13.1.3 I²S Mode

6.3.13.3.1 I²C Control Mode

Table 6-35 Page 0 / Register 4 (0x04): Clock-Gen Muxing⁽¹⁾

Table 6-38 Page 0 / Register 7 (0x07): PLL D-Value MSB⁽¹⁾

Table 6-39 Page 0 / Register 8 (0x08): PLL D-Value LSB⁽¹⁾

Table 6-44 Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB⁽²⁾⁽¹⁾

Table 6-55 Page 0 / Register 34 (0x22): I²C Bus Condition