SLAS666B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
The audio interface of the can enter DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
For the DSP mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data.