SBOS756 October   2016 TLV3541 , TLV3542 , TLV3544

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV3541
    5. 6.5 Thermal Information: TLV3542
    6. 6.6 Thermal Information: TLV3544
    7. 6.7 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Rail-to-Rail Output
      4. 7.3.4 Output Drive
      5. 7.3.5 Video
      6. 7.3.6 Driving Analog-to-Digital Converters
      7. 7.3.7 Capacitive Load and Stability
      8. 7.3.8 Wideband Transimpedance Amplifier
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
    1. 9.1 Input and ESD Protection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply voltage, V+ to V− 7.5 V
Signal input terminals(2) (V–) – (0.5) (V+) + 0.5 V
Current Signal input terminals(2) –10 10 mA
Output short circuit(3) Continuous
Temperature Operating, TA –55 150 °C
Junction, TJ –65 150 °C
Storage, Tstg 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage, V– to V+ 2.5 5.5 V
Specified temperature range –40 125 °C

6.4 Thermal Information: TLV3541

THERMAL METRIC(1) TLV3541 UNIT
D (SOIC) DBV (SOT-23)
8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 123.8 216.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 68.7 84.3 °C/W
RθJB Junction-to-board thermal resistance 64.5 43.1 °C/W
ψJT Junction-to-top characterization parameter 23.0 3.8 °C/W
ψJB Junction-to-board characterization parameter 64.0 42.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

6.5 Thermal Information: TLV3542

THERMAL METRIC(1) TLV3542 UNIT
D (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 113.9 175.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 60.4 67.8 °C/W
RθJB Junction-to-board thermal resistance 54.1 97.1 °C/W
ψJT Junction-to-top characterization parameter 17.1 9.3 °C/W
ψJB Junction-to-board characterization parameter 53.6 95.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

6.6 Thermal Information: TLV3544

THERMAL METRIC(1) TLV3544 UNIT
D (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 83.8 92.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 70.7 27.5 °C/W
RθJB Junction-to-board thermal resistance 59.5 33.6 °C/W
ψJT Junction-to-top characterization parameter 11.6 1.9 °C/W
ψJB Junction-to-board characterization parameter 37.7 33.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

6.7 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply

at TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V, at TA = 25°C ±2 ±10 mV
dVOS/dT Input offset voltage vs temperature VS = 5 V, at TA = −40°C to +125°C ±4.5 μV/°C
PSRR Input offset voltage vs power supply VS = 2.7 V to 5.5 V,
VCM = (VS / 2) − 0.55 V		 60 70 dB
INPUT BIAS CURRENT
IB Input bias current 3 pA
IOS Input offset current ±1 pA
NOISE
en Input voltage noise density f = 1 MHz 7.5 nV/√Hz
in Current noise density f = 1 MHz 50 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V−) − 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 5.5 V, –0.1 V < VCM < 3.5 V,
at TA = 25°C		 66 80 dB
VS = 5.5 V, –0.1 V < VCM < 5.6 V,
at TA = 25°C		 56 68 dB
INPUT IMPEDANCE
Differential 1013 || 2 Ω || pF
Common-mode 1013 || 2 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop gain VS = 5 V, 0.3 V < VO < 4.7 V,
at TA = 25°C		 92 108 dB
FREQUENCY RESPONSE
f−3dB Small-signal bandwidth At G = +1, VO = 10 mV
RF = 25 Ω		 200 MHz
At G = +2, VO = 10 mV 90 MHz
GBW Gain-bandwidth product G = +10 100 MHz
f0.1dB Bandwidth for 0.1-dB gain flatness At G = +2, VO = 10 mV 40 MHz
SR Slew rate VS = 5 V, G = +1, 4-V step 150 V / μs
VS = 5 V, G = +1, 2-V step 130 V / μs
Rise-and-fall time At G = +1, VO = 200 mVPP,
10% to 90%		 2 ns
At G = +1, VO = 2 VPP, 10% to 90% 11 ns
Settling time 0.1%, VS = 5 V, G = +1,
2-V output step		 30 ns
0.01%, VS = 5 V, G = +1,
2-V output step		 60 ns
Overload recovery time VIN × Gain = VS 5 ns
FREQUENCY RESPONSE, continued
Harmonic distortion Second harmonic At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V		 –75 dBc
Third harmonic At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V		 –83 dBc
Differential gain error NTSC, RL = 150 Ω 0.02%
Differential phase error NTSC, RL = 150 Ω 0.09 °
Channel-to-channel crosstalk TLV3542 f = 5 MHz –100 dB
TLV3544 –84 dB
OUTPUT
Voltage output swing from rail VS = 5 V, RL = 1 kΩ at TA = 25°C 0.1 0.3 V
IO Output current, single, dual, quad(1)(2) VS = 5 V 100 mA
VS = 3 V 50 mA
Closed-loop output impedance f < 100 kHz 0.05 Ω
RO Open-loop output resistance 35 Ω
POWER SUPPLY
VS Specified voltage range 2.7 5.5 V
Operating voltage range 2.5 5.5 V
IQ Quiescent current (per amplifier) At TA = 25°C, VS = 5 V,
IO = 0		 5.2 6.5 mA
TEMPERATURE RANGE
Specified range –40 125 °C
Operating range (3) –55 150 °C
Storage range –65 150 °C
THERMAL SHUTDOWN
Shutdown temperature 160 °C
Reset from shutdown 140 °C
(1) See typical characteristic curves, Output Voltage Swing vs Output Current (Figure 14 and Figure 15).
(2) Specified by design.
(3) Operating in this temperature range will not damage the part. However, degraded performance may be observed.

6.8 Typical Characteristics

at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2, unless otherwise noted.
TLV3541 TLV3542 TLV3544 C200_SBOS756.png
RF = 604 ‎Ω VO = 10 mVpp
Figure 2. Noninverting Small-Signal Frequency Response
TLV3541 TLV3542 TLV3544 tc_noninverting_sm-signal_step_resp_bos233.gif
Figure 4. Noninverting Small-Signal Step Response
TLV3541 TLV3542 TLV3544 C201_SBOS756.png
G = +1, RF = 0 ‎Ω VO = 10 mVpp CL = 0 pF
Figure 6. Frequency Response for Various RL
TLV3541 TLV3542 TLV3544 tc_recommended_rs_cload_bos756.gif
Figure 8. Recommended RS vs Capacitive Load
TLV3541 TLV3542 TLV3544 tc_cmrr_psrr_fqcy_bos233.gif
Figure 10. Common-Mode Rejection Ratio and Power-Supply Rejection Ratio vs Frequency
TLV3541 TLV3542 TLV3544 tc_differential_gain_phase_bos233.gif
Figure 12. Composite Video Differential Gain and Phase
TLV3541 TLV3542 TLV3544 tc_3V_vout_swing_iout_bos233.gif
Figure 14. Output Voltage Swing vs Output Current
for VS = 3 V
TLV3541 TLV3542 TLV3544 tc_closed_loop_output_imped_fqcy_bos756.gif
Figure 16. Closed-Loop Output Impedance vs Frequency
TLV3541 TLV3542 TLV3544 tc_output_settling_time_bos233.gif
Figure 18. Output Settling Time to 0.1%
TLV3541 TLV3542 TLV3544 tc_crosstalk_bos756.gif
Figure 20. Channel-to-Channel Crosstalk
TLV3541 TLV3542 TLV3544 tc_inverting_sm-signal_fqcy_resp_bos233.gif
Figure 3. Inverting Small-Signal Frequency Response
TLV3541 TLV3542 TLV3544 tc_noninverting_lg-signal_step_resp_bos233.gif
Figure 5. Noninverting Large-Signal Step Response
TLV3541 TLV3542 TLV3544 C202_SBOS756.png
G = +1, RS = 0 ‎Ω VO = 10 mVpp
Figure 7. Frequency Response for Various CL
TLV3541 TLV3542 TLV3544 C203_SBOS756.png
G = +1, VO = 10 mVpp
Figure 9. Frequency Response vs Capacitive Load
TLV3541 TLV3542 TLV3544 tc_open_loop_gain_phase_bos233.gif
Figure 11. Open-Loop Gain and Phase
TLV3541 TLV3542 TLV3544 tc_ibias_temp_bos233.gif
Figure 13. Input Bias Current vs Temperature
TLV3541 TLV3542 TLV3544 tc_5V_vout_swing_iout_bos233.gif
Figure 15. Output Voltage Swing vs Output Current
for VS = 5 V
TLV3541 TLV3542 TLV3544 tc_vout_max_fqcy_bos233.gif
Figure 17. Maximum Output Voltage vs Frequency
TLV3541 TLV3542 TLV3544 tc_voffset_prod_distribution_bos233.gif
Figure 19. Offset Voltage Production Distribution