SNVSB04B March   2019  – June 2020 TLV4021 , TLV4031 , TLV4041 , TLV4051

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      TLV40x1 Configurations
  4. Revision History
  5. Pin Configuration and Functions
    1.     DSBGA Package Pin Functions
    2.     SOT-23 Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power ON Reset (POR)
      2. 7.4.2 Input (IN)
      3. 7.4.3 Switching Thresholds and Hysteresis (VHYS)
      4. 7.4.4 Output (OUT)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Monitoring (V+)
      2. 8.1.2 Monitoring a Voltage Other than (V+)
      3. 8.1.3 VPULLUP to a Voltage Other than (V+)
    2. 8.2 Typical Application
      1. 8.2.1 Under-Voltage Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Additional Application Information
        1. 8.2.2.1 Pull-up Resistor Selection
        2. 8.2.2.2 Input Supply Capacitor
        3. 8.2.2.3 Sense Capacitor
    3. 8.3 What to Do and What Not to Do
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

Configure the circuit as shown in Figure 44. Connect (V+) to 3.3 V which also powers the micro-controller. Resistors R1 and R2 create the under-voltage alert level of 2.0 V. When the battery voltage sags down to 2.0 V, the resistor divider voltage crosses the (VIT-) threshold of the TLV4041R1. This causes the comparator output to transition from a logic high to a logic low. The push-pull option of the TLV40x1 family is selected since the comparator operating voltage is shared with the microcontroller which is receiving the under-voltage alert signal. The TLV4041 option with the 1.2 V internal reference is selected because it is the closest internal reference option that is less than the critical under-voltage level of 2.0 V. Choosing the internal reference option that is closest to the critical under-voltage level minimizes the resistor divider ratio which optimizes the accuracy of the circuit. Error at the falling edge threshold of (VIT-) is amplified by the inverse of the resistor divider ratio. So minimizing the resistor divider ratio is a way of optimizing voltage monitoring accuracy.

Equation 1 is derived from the analysis of Figure 44.

Equation 1. TLV4021 TLV4031 TLV4041 TLV4051 VITn.gif

where

  • R1 and R2 are the resistor values for the resistor divider connected to IN
  • VBAT is the voltage source that is being monitored for an undervoltage condition.
  • VIT- is the falling edge threshold where the comparator output changes state from high to low

Rearranging Equation 1 and solving for R1 yields Equation 2.

Equation 2. TLV4021 TLV4031 TLV4041 TLV4051 UV_eqn.gif

For the specific undervoltage detection of 2.0 V using the TLV4041R1, the following results are calculated.

Equation 3. TLV4021 TLV4031 TLV4041 TLV4051 UV_eqnval.gif

where

  • R2 is set to 1 MΩ
  • VBAT is set to 2.0 V
  • VIT- is set to1.18 V

Choose RTOTAL (R1 + R2) such that the current through the divider is at least 100 times higher than the input bias current (IBIAS). The resistors can have high values to minimize current consumption in the circuit without adding significant error to the resistive divider.