SNVSB04B March   2019  – June 2020 TLV4021 , TLV4031 , TLV4041 , TLV4051

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      TLV40x1 Configurations
  4. Revision History
  5. Pin Configuration and Functions
    1.     DSBGA Package Pin Functions
    2.     SOT-23 Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power ON Reset (POR)
      2. 7.4.2 Input (IN)
      3. 7.4.3 Switching Thresholds and Hysteresis (VHYS)
      4. 7.4.4 Output (OUT)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Monitoring (V+)
      2. 8.1.2 Monitoring a Voltage Other than (V+)
      3. 8.1.3 VPULLUP to a Voltage Other than (V+)
    2. 8.2 Typical Application
      1. 8.2.1 Under-Voltage Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Additional Application Information
        1. 8.2.2.1 Pull-up Resistor Selection
        2. 8.2.2.2 Input Supply Capacitor
        3. 8.2.2.3 Sense Capacitor
    3. 8.3 What to Do and What Not to Do
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

The TLV40x1 devices are low-power comparators that are well suited for compact, low-current, precision voltage detection applications. With high-accuracy, switching thresholds options of 0.2V, 0.5 V, 1.2V, and 3.2V, 2uA of quiescent current, and propagation delay of 450ns and 2us, the TLV40x1 comparator family enables power conscious systems to monitor and respond quickly to fault conditions.

The TLV40x1Ry comparators assert the output signal as shown in Table 2. VIT+ represents the positive-going input threshold that causes the comparator output to change state, while VIT- represents the negative-going input threshold that causes the output to change state. Since VIT+ and VIT- are factory trimmed and warranted over temperature, the TLV40x1 is equally suited for undervoltage and overvoltage applications. In order to monitor any voltage above the internal reference voltage, an external resistor divider network is required.

The TLV4021S5 functions similar to the TLV40x1Ry comparators except the resistor divider is internal to the device. Having the resistor divider internal to the device allows the TLV4021S5 to have switching thresholds higher than the internal reference voltage of 1.2V without any external components.

Table 2. TLV40x1 Truth Table

DEVICE (VIT+, VIT-) OUTPUT TOPOLOGY INPUT VOLTAGE OUTPUT LOGIC LEVEL
TLV4021R2
TLV4021R1
0.2V, 0.18V
1.2V, 1.18V
Open-Drain IN > VIT+ Output high impedance
IN < VIT- Output asserted low
TLV4041R2
TLV4041R5
TLV4041R1
0.2V, 0.18V
0.5V, 0.48V
1.2V, 1.18V
Push-Pull IN > VIT+ Output asserted high
IN < VIT- Output asserted low
TLV4031R2
TLV4031R1
0.2V, 0.18V
1.2V, 1.18V
Open-Drain IN > VIT+ Output asserted low
IN < VIT- Output high impedance
TLV4051R2
TLV4051R5
TLV4051R1
0.2V, 0.18V
0.5V, 0.48V
1.2V, 1.18V
Push-Pull IN > VIT+ Output asserted low
IN < VIT- Output asserted high
TLV4021S5 3.254V, 3.2V Open-Drain IN > VIT+ Output high impedance
IN < VIT- Output asserted low