SBOS753B June   2016  – February 2017 TLV2313 , TLV313 , TLV4313

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TLV313
    5. 7.5  Thermal Information: TLV2313
    6. 7.6  Thermal Information: TLV4313
    7. 7.7  Electrical Characteristics: 5.5 V
    8. 7.8  Electrical Characteristics: 1.8 V
    9. 7.9  Typical Characteristics: Table of Graphs
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Input
      3. 8.3.3 Rail-to-Rail Output
      4. 8.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5 Capacitive Load and Stability
      6. 8.3.6 EMI Susceptibility and Input Filtering
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
    1. 10.1 Input and ESD Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply voltage 7 V
Signal input terminals(2) (V−) − (0.5) (V+) + 0.5 V
Current Signal input terminals(2) –10 10 mA
Output short circuit(3) Continuous
Temperature Operating, TA –40 150 °C
Junction, TJ 150 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage 1.8 5.5 V
TA Specified temperature range –40 125 °C

7.4 Thermal Information: TLV313

THERMAL METRIC(1) TLV313 UNIT
DBV (SOT23) DCK (SC70)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 228.5 281.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 99.1 91.6 °C/W
RθJB Junction-to-board thermal resistance 54.6 59.6 °C/W
ψJT Junction-to-top characterization parameter 7.7 1.5 °C/W
ψJB Junction-to-board characterization parameter 53.8 58.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information: TLV2313

THERMAL METRIC(1) TLV2313 UNIT
D (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 138.4 191.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 89.5 61.9 °C/W
RθJB Junction-to-board thermal resistance 78.6 111.9 °C/W
ψJT Junction-to-top characterization parameter 29.9 5.1 °C/W
ψJB Junction-to-board characterization parameter 78.1 110.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

7.6 Thermal Information: TLV4313

THERMAL METRIC(1) TLV4313 UNIT
PW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 121.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.4 °C/W
RθJB Junction-to-board thermal resistance 62.8 °C/W
ψJT Junction-to-top characterization parameter 5.9 °C/W
ψJB Junction-to-board characterization parameter 62.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

7.7 Electrical Characteristics: 5.5 V


At TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.75 3 mV
dVOS/dT Input offset voltage vs temperature TA = –40°C to 125°C 2 μV/°C
PSRR Power-supply rejection ratio 74 90 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 85 dB
VCM = –0.2 V to 5.7 V 64 80 dB
INPUT BIAS CURRENT
IB Input bias current ±1 pA
IOS Input offset current ±1 pA
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 6 μVPP
en Input voltage noise density f = 10 kHz 22 nV/√Hz
f = 1 kHz 26 nV/√Hz
in Input current noise density f = 1 kHz 5 fA/√Hz
INPUT CAPACITANCE
CIN Differential 1 pF
Common-mode 5 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain 0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ 104 dB
0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ 100 110 dB
Phase margin VS = 5.0 V, G = +1 65 °
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 5.0 V, CL = 10 pF 1 MHz
SR Slew rate VS = 5.0 V, G = +1 0.5 V/μs
tS Settling time To 0.01%, VS = 5.0 V, 2-V step , G = +1 6 μs
Overload recovery time VS = 5.0 V, VIN × Gain > VS 3 μs
OUTPUT
VO Voltage output swing from supply rails RL = 100 kΩ(2) 5 20 mV
RL = 2 kΩ(2) 75 100 mV
ISC Short-circuit current ±15 mA
RO Open-loop output impedance 2300 Ω
POWER SUPPLY
VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V
IQ Quiescent current per amplifier TA = –40°C to 125°C, VS = 5.0 V, IO = 0 mA 65 90 µA
Power-on time VS = 0 V to 5 V, to 90% IQ level 10 µs
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over-temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.

7.8 Electrical Characteristics: 1.8 V


At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS+ – 1.3 V, and VOUT = VS / 2, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.75 3 mV
dVOS/dT Input offset voltage vs temperature TA = –40°C to 125°C 2 μV/°C
PSRR Power-supply rejection ratio 74 90 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 85 dB
VCM = –0.2 V to +1.8 V 73 dB
INPUT BIAS CURRENT
IB Input bias current ±1 pA
IOS Input offset current ±1 pA
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 6 μVPP
en Input voltage noise density f = 10 kHz 22 nV/√Hz
f = 1 kHz 26 nV/√Hz
in Input current noise density f = 1 kHz 5 fA/√Hz
INPUT CAPACITANCE
CIN Differential 1 pF
Common-mode 5 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain 0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ 110 dB
0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ 110 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product CL = 10 pF 0.9 MHz
SR Slew rate G = +1 0.45 V/μs
tS Settling time To 0.01%, VS = 5.0 V, 2-V step , G = +1 6 μs
Overload recovery time VS = 5.0 V, VIN × Gain > VS 3 μs
OUTPUT
VO Voltage output swing from supply rails RL = 100 kΩ(2) 5 mV
RL = 2 kΩ(2) 25 mV
ISC Short-circuit current ±6 mA
RO Open-loop output impedance 2300 Ω
POWER SUPPLY
VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V
IQ Quiescent current per amplifier TA = –40°C to 125°C, VS = 5.0 V, IO = 0 mA 65 90 µA
Power-on time VS = 0 V to 5 V, to 90% IQ level 10 µs
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over-temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.

7.9 Typical Characteristics: Table of Graphs

Table 1. Table of Graphs

TITLE FIGURE
Open-Loop Gain and Phase vs Frequency Figure 1
Quiescent Current vs Supply Voltage Figure 2
Offset Voltage Production Distribution Figure 3
Offset Voltage vs Common-Mode Voltage (Maximum Supply) Figure 4
CMRR and PSRR vs Frequency (RTI) Figure 5
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V) Figure 6
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V) Figure 7
Input Bias and Offset Current vs Temperature Figure 8
Open-Loop Output Impedance vs Frequency Figure 9
Maximum Output Voltage vs Frequency and Supply Voltage Figure 10
Output Voltage Swing vs Output Current (over Temperature) Figure 11
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V) Figure 12
Small-Signal Step Response, Noninverting (1.8 V) Figure 13
Small-Signal Step Response, Noninverting ( 5.5 V) Figure 14
Large-Signal Step Response, Noninverting (1.8 V) Figure 15
Large-Signal Step Response, Noninverting ( 5.5 V) Figure 16
No Phase Reversal Figure 17
EMIRR IN+ vs Frequency Figure 18

7.10 Typical Characteristics

At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
TLV313 TLV2313 TLV4313 tc_open_loop_gain_phase-fqcy_bos779.gif
Figure 1. Open-Loop Gain and Phase vs Frequency
TLV313 TLV2313 TLV4313 C005_SBOS649.png
Figure 3. Offset Voltage Production Distribution
TLV313 TLV2313 TLV4313 C009_SBOS649.png
Figure 5. CMRR and PSRR vs Frequency
(Referred-to-Input)
TLV313 TLV2313 TLV4313 C012_SBOS649.png
Figure 7. Input Voltage Noise Spectral Density vs Frequency
TLV313 TLV2313 TLV4313 C015_SBOS649.png
Figure 9. Open-Loop Output Impedance vs Frequency
TLV313 TLV2313 TLV4313 C017_SBOS649.png
Figure 11. Output Voltage Swing vs Output Current (Over Temperature)
TLV313 TLV2313 TLV4313 C022_SBOS649.png
Figure 13. Small-Signal Pulse Response
(Minimum Supply)
TLV313 TLV2313 TLV4313 C024_SBOS649.png
Figure 15. Large-Signal Pulse Response
(Minimum Supply)
TLV313 TLV2313 TLV4313 C028_SBOS649.png
Figure 17. No Phase Reversal
TLV313 TLV2313 TLV4313 C003_SBOS649.png
Figure 2. Quiescent Current vs Supply
TLV313 TLV2313 TLV4313 C007_SBOS649.png
Figure 4. Offset Voltage vs Common-Mode Voltage
TLV313 TLV2313 TLV4313 C011_SBOS649.png
Figure 6. 0.1-Hz to 10-Hz Input Voltage Noise
TLV313 TLV2313 TLV4313 C014_SBOS649.png
Figure 8. Input Bias and Offset Current vs Temperature
TLV313 TLV2313 TLV4313 C016_SBOS649.png
Figure 10. Maximum Output Voltage vs Frequency and Supply Voltage
TLV313 TLV2313 TLV4313 C018_SBOS649.png
Figure 12. Closed-Loop Gain vs Frequency (Minimum Supply)
TLV313 TLV2313 TLV4313 C023_SBOS649.png
Figure 14. Small-Signal Pulse Response
(Maximum Supply)
TLV313 TLV2313 TLV4313 C025_SBOS649.png
Figure 16. Large-Signal Pulse Response
(Maximum Supply)
TLV313 TLV2313 TLV4313 C033_SBOS649.png
Figure 18. EMIRR IN+ vs Frequency