SNOSD27 May   2016 TLV522

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Rail-To-Rail Input
      2. 7.4.2 Supply Current Changes Over Common Mode
      3. 7.4.3 Design Optimization With Rail-To-Rail Input
      4. 7.4.4 Design Optimization for Nanopower Operation
      5. 7.4.5 Common-Mode Rejection
      6. 7.4.6 Output Stage
      7. 7.4.7 Driving Capacitive Load
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: 60 Hz Twin "T" Notch Filter
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Supply voltage, V+ to V– -0.3 6 V
Signal input pins Voltage(2) V- – 0.3 V+ + 0.3 V
Current(2) –10 10 mA
Output short current Continuous(4)
Junction temperature –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current-limited to 10 mA or less.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(4) Short-circuit to V–.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)		 ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Ratings

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply Voltage ( V+– V− ) 1.7 5.5 V
Specified Temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TLV522 UNIT
DGK (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 182.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.6
RθJB Junction-to-board thermal resistance 104.1
ψJT Junction-to-top characterization parameter 13.7
ψJB Junction-to-board characterization parameter 102.5
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
OFFSET VOLTAGE
Input offset voltage (VOS) VCM = 0.3 V –4 ±1 4 mV
VCM = 3 V –4 ±1 4
Drift (dVOS/dT) 1.5 µV/°C
Power-Supply Rejection Ratio (PSRR) V+ = 1.8 V to 3.3 V, VCM = 0.3 V 80 109 dB
INPUT VOLTAGE RANGE
Common-Mode voltage range (VCM) CMRR ≥ 62 dB 0 3.3 V
Common-Mode Rejection Ratio (CMRR) 0 V < VCM < 3.3 V 62 90 dB
0 V < VCM < 2.2V 90
INPUT BIAS CURRENT
Input bias current (IBIAS) ±1 pA
Input offset current (IOS) ±0.1
INPUT IMPEDANCE
Differential 1013 || 2.5 Ω || pF
Common mode 1013 || 2.5
NOISE
Input voltage noise density, f = 1 kHz (en) 300 nV/√Hz
Current noise density, f = 1 kHz (in) 65 fA√Hz
OPEN-LOOP GAIN
Open-loop voltage gain (AOL) V+ = 5 V
RL = 100 kΩ to V+/2, 0.5 V < VO < 4.5 V 		91 101 dB
OUTPUT
Voltage output swing from positive rail V+ = 1.8 V, RL = 100 kΩ to V+/2 3 20 mV
Voltage output swing from negative rail V+ = 1.8 V, RL = 100 kΩ to V+/2 2 20
Output current sourcing Sourcing, V+ = 1.8 V
VO to V–, VIN(diff) = 100 mV		 1 3 mA
Output current sinking Sinking, V+ = 1.8 V
VO to V+, VIN(diff) = –100 mV		 1 5
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP) CL = 20 pF 8 kHz
Slew rate (SR) G = +1, Rising edge, 1Vp-p, CL = 20 pF 3.6 V/ms
G = +1, Falling edge, 1Vp-p, CL = 20 pF 3.7
POWER SUPPLY
Quiescent current per channel (IQ) VCM = 0.3 V, IO = 0 500 800 nA

6.6 Typical Characteristics

TA = 25 °C, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
TLV522 IsVs_LowVcm.png
No Output Load VCM = 0.3 V
Figure 1. Supply Voltage vs Supply Current per Channel,
Low Vcm
TLV522 IsVcm_3p3.png
No Output Load
Figure 3. Supply Current vs
Common Mode at 3.3 V
TLV522 Source_3p3V.png
VS = 3.3 V
Figure 5. Output Sourcing Current vs
Output Swing at 3.3 V
TLV522 SHRT_CKT_2VS.png
Ouput set low (sinking), shorted to V+
Figure 7. Output Short Circuit Current to V+ vs
Supply Voltage
TLV522 IB_VCM_3p3_85_GRAF.gif
VS = 3.3 V TA = 85°C
Figure 9. Input Bias Current vs
Common Mode Voltage at 3.3 V
TLV522 Noise_5V.png
VS = 5 V RL = 100 kΩ CL = 20 pF
Figure 11. Input Referred Voltage Noise
TLV522 PulseResp_1p8V_1V.png
VS = ±0.9 V RL = 10 MΩ CL = 20 pF
G = +1 VIN = ±500mV
Figure 13. Pulse Response, 1Vpp at 1.8V
TLV522 PulseResp_5V_2V.png
VS = ±2.5 V RL = 10 MΩ CL = 20 pF
G = +1 VIN = ±1V
Figure 15. Pulse Response, 2Vpp at 5V
TLV522 AVPH_5V_vsTemp_100k.png
VS = 5 V RL = 100 kΩ CL = 20 pF
Figure 17. Gain and Phase vs
Temperature at 5 V
TLV522 AVPH_5V_vsTemp_1M.png
VS = 5 V RL = 1 MΩ CL = 20 pF
Figure 19. Gain and Phase vs
Temperature at 5 V
TLV522 AVPH_5V_vsTemp_10M.png
VS = 5 V RL = 10 MΩ CL = 20 pF
Figure 21. Gain and Phase vs
Temperature at 5 V
TLV522 IsVs_HiVcm.png
No Output Load VCM = (V+) – 0.3 V
Figure 2. Supply Voltage vs Supply Current per Channel,
High Vcm
TLV522 Sink_3p3V.png
VS = 3.3 V
Figure 4. Output Sinking Current vs
Output Swing at 3.3 V
TLV522 SHRT_CKT_2GND.png
Output set high (sourcing), shorted to V–
Figure 6. Output Short Circuit Current to V- vs
Supply Voltage
TLV522 IB_VCM_3p3_25_GRAF.gif
VS = 3.3 V TA = 25°C
Figure 8. Input Bias Current vs
Common Mode Voltage at 3.3 V
TLV522 IB_VCM_3p3_125_GRAF.gif
VS = 3.3 V TA = 125°C
Figure 10. Input Bias Current vs
Common Mode Voltage at 3.3 V
TLV522 PulseResp_1p8V_200mV.png
VS = ±0.9 V RL = 10 MΩ CL = 20 pF
G = +1 VIN = ±100 mV
Figure 12. Pulse Response, 200mVpp at 1.8 V
TLV522 PulseResp_5V_200mV.png
VS = ±2.5 V RL = 10 MΩ CL = 20 pF
G = +1 VIN = ±100 mV
Figure 14. Pulse Response, 200mVpp at 5V
TLV522 AVPH_1p8V_vsTemp_100k.png
VS = 1.8 V RL = 100 kΩ CL = 20 pF
Figure 16. Gain and Phase vs
Temperature at 1.8 V
TLV522 AVPH_1p8V_vsTemp_1M.png
VS = 1.8 V RL = 1 MΩ CL = 20 pF
Figure 18. Gain and Phase vs
Temperature at 1.8 V
TLV522 AVPH_1p8V_vsTemp_10M.png
VS = 1.8 V RL = 10 MΩ CL = 20 pF
Figure 20. Gain and Phase vs
Temperature at 1.8 V