SNOSDM1 December   2025 TLV6722

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Separate Power Supplies (H_VCC, M_VCC)
      2. 8.4.2 Low Supply Reset Deassertion
      3. 8.4.3 Power-On Reset (POR)
      4. 8.4.4 Inputs (INT/RSTn, LPWn/PRSn(/ePPS), M_INT)
      5. 8.4.5 Outputs (M_RSTn, M_LPWn, M_CLK)
      6. 8.4.6 Switching Thresholds and Hysteresis
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Comparison

Table 4-1 Device Comparison
DEVICE NAMEDESCRIPTION
TLV6722OSFP/OSFP-XD Module Low Speed Signals Controller with no clock buffer output. The clock buffer is permanently disabled. This device is well-suited for OSFP and OSFP-XD applications where ePPS/reference clock support is not required.
TLV6723OSFP/OSFP-XD Module Low Speed Signals Controller with self-shutdown clock buffer. The clock buffer enters a self-shutdown mode to draw less supply current whenever LPWn/PRSn/ePPS is in MSA voltage Zone 1. When LPWn/PRSn/ePPS is in MSA voltage Zone 2, the clock buffer turns on and is ready to receive ePPS/reference clock signals.
TLV6724OSFP/OSFP-XD Module Low Speed Signals Controller with always-on clock buffer. The clock buffer is always on regardless of LPWn/PRSn/ePPS voltage zone.
INT/RSTn Truth Table
INT/RSTn (V) Voltage Zone M_RSTn M_INT
Min Nom Max
0.000 0.000 1.000 Zone 1 LOW X
1.500 1.900 2.250 Zone 2 HIGH LOW
2.750 3.000 3.465 Zone 3 HIGH HIGH
LPWn/PRSn(/ePPS) Truth Table
LPWn/PRSn(/ePPS) (V) Voltage Zone M_LPWn
Min Nom Max
0.000 0.950 1.100 Zone 1 LOW
1.400 1.700 2.250 Zone 2 HIGH