SBVS153G february   2011  – june 2023 TLV707 , TLV707P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Dropout Voltage
        3. 8.2.2.3 Transient Response
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 8.5.1.2 Package Mounting
        3. 8.5.1.3 Thermal Considerations
        4. 8.5.1.4 Power Dissipation
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater); IOUT = 1 mA, VEN = VIN, COUT = 0.47 μF, and TJ = –40°C to +85°C (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Output voltage range 0.85 5 V
DC output accuracy 0.5%
VOUT ≥ 0.85 V –1.5% 1.5%
ΔVO(ΔVI) Line regulation 1 5 mV
ΔVO(ΔIO) Load regulation 0 mA ≤ IOUT ≤ 150 mA 10 20 mV
V(DO) Dropout voltage VIN = 0.98 x VOUT(nom) 2.0 V < VOUT ≤ 2.4 V IOUT = 30 mA 65 mV
IOUT = 150 mA 325 360
2.4 V < VOUT ≤ 2.8 V IOUT = 30 mA 50
IOUT = 150 mA 250 300
2.8 V < VOUT ≤ 3.3 V IOUT = 30 mA 45
IOUT = 150 mA 220 270
3.3 V < VOUT ≤ 5.0 V IOUT = 30 mA 40
IOUT = 150 mA 200 250
V(DO) Dropout voltage, TLV707xxA VIN = 0.98 × VOUT(nom) 2.0 V < VOUT ≤ 2.5 V IOUT = 30 mA 65 mV
IOUT = 150 mA 325 360
2.5 V < VOUT ≤ 3.1 V IOUT = 30 mA 50
IOUT = 150 mA 250 300
3.1 V < VOUT ≤ 3.5 V IOUT = 30 mA 45
IOUT = 150 mA 220 280
3.5 V < VOUT ≤ 5.0 V IOUT = 30 mA 40
IOUT = 150 mA 200 260
ICL Output current limit VOUT = 0.9 × VOUT(nom) 240 300 450 mA
ICL Output current limit, TLV707xxA VOUT = 0.9 × VOUT(nom), VOUT(nom) ≤ 1.5 V 220 300 450 mA
VOUT = 0.9 × VOUT(nom), VOUT(nom) > 1.5 V 240 300 450
I(GND) Ground pin current IOUT = 0 mA 25 50 µA
I(EN) EN pin current VEN = 5.5 V 0.01 µA
ISHUTDOWN Shutdown current VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V 1 µA
VIL(EN) EN pin low-level input voltage (disable device) 0 0.4 V
VIH(EN) EN pin high-level input voltage (enable device) 0.9 VIN V
PSRR Power-supply rejection ratio VIN = 3.3 V, VOUT = 2.8 V,
IOUT = 30 mA		 f = 100 Hz 70 dB
f = 10 kHz 55
f = 1 MHz 50
Vn Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V,
IOUT = 10 mA		 45 µVRMS
tSTR Start-up time(1) COUT = 1.0 µF, IOUT = 150 mA 100 µs
RPULLDOWN Pulldown resistance
(TLV707P only)		 120 Ω
(1) Start-up time = time from EN assertion to 0.98 × VOUT.