SLDS151A May   2009  – June 2015 TMP814

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Speed Control
      2. 7.3.2 Constant Voltage Bias
      3. 7.3.3 Soft-Start
      4. 7.3.4 Lock Detection
      5. 7.3.5 Current Limit
      6. 7.3.6 Minimum Speed Setting
      7. 7.3.7 Speed Output
      8. 7.3.8 Drive Frequency Selection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 12-V Sample Application Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 24-V/48-V Sample Application Circuit
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
20-Pin TSSOP
Top View
TMP814 pinout_lds151.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 OUT2P O Upper-side driver output
2 OUT2N O Lower-side driver output
3 VCC Power supply. For the CM capacitor that is a power stabilization capacitor for PWM drive and for absorption of kickback, the capacitance of 0.1 μF to 1 μF is used. In this device, the lower TR performs current regeneration by switching the upper TR. Connect CM between VCC and GND, with the thick pattern and along the shortest route. Use a zener diode if kickback causes excessive increase of the supply voltage, because such increase may damage the device.
4 VLIM I Activates the current limiter when SENSE voltage is greater than VLIM voltage. Connect to 6VREG when not used.
5 SENSE I Sense input. Connect to GND when not used.
6 RMI I Minimum speed setting. Connect to 6VREG when not used. If device power can be removed before power is removed from RMI, insert a current limiting resistor to prevent inflow of large current.
7 VTH I VTH : Connect to GND if not used (Full Speed).
8 CPWM O Connect to capacitor CP to set the PWM oscillation frequency. With CP = 100 pF, oscillation occurs at 25 kHz and provides the basic frequency of PWM.
9 FG O Open collector output, which can detect the rotation speed using the FG output according to the phase shift. Leave open when not used.
10 RD O Open collector output. Outputs low during rotation and high at stop. Leave open when not used.
11 IN– I Hall input
12 HB O This is a Hall element bias, that is, the 1.5-V constant-voltage output.
13 IN+ I Hall input. Make connecting traces as short as possible to prevent carrying of noise. To futher limit noise, insert a capacitor between IN+ and IN–. The Hall input circuit is a comparator having a hysteresis of 20 mV. The application should ensure that the Hall input level more than three times (60 mVp-p) this hysteresis.
14 CT O Lock detection time setting. Capacitor CT is connected.
15 ROFF I Sets the soft switching time to cut the reactive current before phase change. Connect to 6VREG when not used.
16 6VREG O 6-V regulator output
17 SGND Connected to the control circuit power supply system.
18 VOVER O Constant-voltage bias and should be used for application of 24 V and 48 V (see Figure 7). A current limiting resistor should be used. Leave open when not used.
19 OUT1N O Lower-side driver output
20 OUT1P O Upper-side driver output