SPRS867A February   2013  – August 2016 TMS320DM369

PRODUCTION DATA.  

  1. 1TMS320DM369 Digital Media System-on-Chip (DMSoC)
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Comparison
    2. 3.2 Device Characteristics
    3. 3.3 Device Compatibility
    4. 3.4 ARM Subsystem Overview
      1. 3.4.1  Components of the ARM Subsystem
      2. 3.4.2  ARM926EJ-S RISC CPU
      3. 3.4.3  CP15
      4. 3.4.4  MMU
      5. 3.4.5  Caches and Write Buffer
      6. 3.4.6  Tightly Coupled Memory (TCM)
      7. 3.4.7  Advanced High-performance Bus (AHB)
      8. 3.4.8  Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      9. 3.4.9  ARM Memory Mapping
        1. 3.4.9.1 ARM Internal Memories
        2. 3.4.9.2 External Memories
      10. 3.4.10 Peripherals
      11. 3.4.11 ARM Interrupt Controller (AINTC)
    5. 3.5 System Control Module
    6. 3.6 Power Management
    7. 3.7 Memory Map Summary
    8. 3.8 Pin Assignments
      1. 3.8.1 Pin Map (Bottom View)
    9. 3.9 Terminal Functions
  4. 4Device Configurations
    1. 4.1 System Module Registers
    2. 4.2 Boot Modes
      1. 4.2.1 Boot Modes Overview
    3. 4.3 Device Clocking
      1. 4.3.1 Overview
      2. 4.3.2 PLL Controller Module
      3. 4.3.3 PLLC1
      4. 4.3.4 PLLC2
      5. 4.3.5 Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies
      6. 4.3.6 PLL Controller Clocking Configurations Examples
      7. 4.3.7 Peripheral Clocking Considerations
    4. 4.4 Power and Sleep Controller (PSC)
    5. 4.5 Pin Multiplexing
    6. 4.6 Device Reset
    7. 4.7 Default Device Configurations
      1. 4.7.1 Device Configuration Pins
      2. 4.7.2 PLL Configuration
      3. 4.7.3 Power Domain and Module State Configuration
      4. 4.7.4 ARM Boot Mode Configuration
      5. 4.7.5 AEMIF Configuration
        1. 4.7.5.1 AEMIF Pin Configuration
        2. 4.7.5.2 AEMIF Timing Configuration
      6. 4.7.6 Oscillator Frequency Configuration
    8. 4.8 Debugging Considerations
      1. 4.8.1 Pullup/Pulldown Resistors
  5. 5System Interconnect
  6. 6Device Operating Conditions
    1. 6.1 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Parameter Information Device-Specific Information
      1. 7.1.1 Signal Transition Levels
      2. 7.1.2 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  Power Supplies
    4. 7.4  Power-Supply Sequencing
      1. 7.4.1 Simple Power-On and Power-Off Method
      2. 7.4.2 Restricted Power-On and Power-Off Method
      3. 7.4.3 Power-Supply Design Considerations
      4. 7.4.4 Power-Supply Decoupling
    5. 7.5  Reset
      1. 7.5.1 Reset Electrical Data/Timing
    6. 7.6  Oscillators and Clocks
      1. 7.6.1 MXI1 Oscillator
      2. 7.6.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)
      3. 7.6.3 PRTCSS Oscillator
      4. 7.6.4 PRTCSS Electrical Data/Timing
    7. 7.7  Power Management and Real Time Clock Subsystem (PRTCSS)
      1. 7.7.1 PRTCSS Peripheral Register Description
    8. 7.8  General-Purpose Input/Output (GPIO)
      1. 7.8.1 GPIO Peripheral Register Description
      2. 7.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 7.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 7.9  EDMA Controller
      1. 7.9.1 EDMA Channel Synchronization Events
      2. 7.9.2 EDMA Peripheral Register Description
    10. 7.10 External Memory Interface (EMIF)
      1. 7.10.1 Asynchronous EMIF (AEMIF)
        1. 7.10.1.1 NAND (NAND, SmartMedia, xD)
        2. 7.10.1.2 OneNAND
        3. 7.10.1.3 EMIF Peripheral Register Descriptions
        4. 7.10.1.4 AEMIF Electrical Data/Timing
      2. 7.10.2 DDR2/mDDR Memory Controller
      3. 7.10.3 DDR2/mDDR Memory Controller Electrical Data/Timing
        1. 7.10.3.1 DDR2/mDDR Routing Specifications
          1. 7.10.3.1.1  DDR2/mDDR Interface
          2. 7.10.3.1.2  DDR2/mDDR Interface Schematic
          3. 7.10.3.1.3  Compatible JEDEC DDR2/mDDR Devices
          4. 7.10.3.1.4  PCB Stack Up
          5. 7.10.3.1.5  Placement
          6. 7.10.3.1.6  DDR2/mDDR Keep Out Region
          7. 7.10.3.1.7  Bulk Bypass Capacitors
          8. 7.10.3.1.8  High-Speed Bypass Capacitors
          9. 7.10.3.1.9  Net Classes
          10. 7.10.3.1.10 DDR2/mDDR Signal Termination
          11. 7.10.3.1.11 VREF Routing
          12. 7.10.3.1.12 DDR2/mDDR CK and ADDR_CTRL Routing
    11. 7.11 MMC/SD
      1. 7.11.1 MMC/SD Peripheral Register Description
      2. 7.11.2 MMC/SD Electrical Data/Timing
    12. 7.12 Video Processing Subsystem (VPSS) Overview
      1. 7.12.1 Video Processing Front-End (VPFE)
        1. 7.12.1.1 Image Sensor Interface (ISIF)
        2. 7.12.1.2 The Image Pipe Interface (IPIPEIF)
        3. 7.12.1.3 Image Pipe - Hardware Image Signal Processor (IPIPE)
        4. 7.12.1.4 Hardware 3A (H3A)
        5. 7.12.1.5 Face Detection Module
        6. 7.12.1.6 VPFE Electrical Data/Timing
      2. 7.12.2 Video Processing Back-End (VPBE)
        1. 7.12.2.1 On-Screen Display (OSD)
        2. 7.12.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD)
        3. 7.12.2.3 VPBE Electrical Data/Timing
        4. 7.12.2.4 High-Definition (HD) DACs and Video Buffer Electrical Data/Timing
          1. 7.12.2.4.1 HD DACs-Only Option
          2. 7.12.2.4.2 DAC With Video Buffer Option
    13. 7.13 USB2.0
      1. 7.13.1 USB Peripheral Register Description
      2. 7.13.2 USB2.0 Electrical Data/Timing
    14. 7.14 Universal Asynchronous Receiver/Transmitter (UART)
      1. 7.14.1 UART Peripheral Register Description
      2. 7.14.2 UART Electrical Data/Timing
    15. 7.15 Serial Port Interface (SPI)
      1. 7.15.1 SPI Peripheral Register Description
      2. 7.15.2 SPI Electrical Data/Timing
        1. 7.15.2.1 Master Mode — General
        2. 7.15.2.2 Slave Mode — General
        3. 7.15.2.3 Master Mode — Additional
        4. 7.15.2.4 Slave Mode — Additional
    16. 7.16 Inter-Integrated Circuit (I2C)
      1. 7.16.1 I2C Peripheral Register Description
      2. 7.16.2 I2C Electrical Data/Timing
        1. 7.16.2.1 Inter-Integrated Circuits (I2C) Timing
    17. 7.17 Multichannel Buffered Serial Port (McBSP)
      1. 7.17.1 McBSP Peripheral Register Description
      2. 7.17.2 McBSP Electrical Data/Timing
        1. 7.17.2.1 multichannel Buffered Serial Port (McBSP) Timing
    18. 7.18 Timer
      1. 7.18.1 Timer Peripheral Register Description
      2. 7.18.2 Timer Electrical Data/Timing
    19. 7.19 Pulse Width Modulator (PWM)
      1. 7.19.1 PWM Peripheral Register Description
      2. 7.19.2 PWM0/1/2/3 Electrical/Timing Data
    20. 7.20 Real Time Out (RTO)
      1. 7.20.1 Real Time Out (RTO) Peripheral Register Description
      2. 7.20.2 RTO Electrical/Timing Data
    21. 7.21 Ethernet Media Access Controller (EMAC)
      1. 7.21.1 EMAC Peripheral Register Description
      2. 7.21.2 Ethernet Media Access Controller (EMAC) Electrical Data/Timing
    22. 7.22 Management Data Input/Output (MDIO)
      1. 7.22.1 MDIO Peripheral Register Description
      2. 7.22.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    23. 7.23 Host-Port Interface (HPI) Peripheral
      1. 7.23.1 HPI Device-Specific Information
      2. 7.23.2 HPI Bus Master
      3. 7.23.3 HPI Peripheral Register Description
      4. 7.23.4 HPI Electrical Data/Timing
    24. 7.24 Key Scan
      1. 7.24.1 Key Scan Peripheral Register Description
        1. 7.24.1.1 Key Scan Registers
      2. 7.24.2 Key Scan Electrical Data/Timing
    25. 7.25 Analog-to-Digital Converter (ADC)
      1. 7.25.1 Analog-to-Digital Converter (ADC) Peripheral Register Description
        1. 7.25.1.1 Analog-to-Digital Converter (ADC) Interface Registers
    26. 7.26 Voice Codec
      1. 7.26.1 Voice Codec Register Description
        1. 7.26.1.1 Voice Codec Registers
    27. 7.27 IEEE 1149.1 JTAG
      1. 7.27.1 JTAG Register Description
      2. 7.27.2 JTAG Test-Port Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Development Tools
    2. 8.2 Device Nomenclature
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information
    2. 9.2 Thermal Data for ZCE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCE|338
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Device Operating Conditions

Table 6-1 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) (1) (2)

Supply voltage ranges All 1.35-V supplies –0.3 V to 1.6 V
All 1.8 V supplies –0.3 V to 2.45 V
All 3.3 V supplies –0.3 V to 3.8 V
Input voltage ranges All 1.8 V I/Os –0.5 V to 2.6 V
All 3.3 V I/Os –0.5 V to 3.8 V
USB_VBUS 0 V to 5.5 V
Operating case temperature ranges Commercial Temperature Tc 0°C to 85 °C
Extended Temperature [D version devices] Tc -40°C to 85 °C
Storage temperature ranges Tstg –55°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.

Table 6-2 Recommended Operating Conditions

NAME DESCRIPTION MIN NOM MAX UNIT
CVDD Core Supply Voltage 432-MHz devices 1.28 1.35 1.42 V
VDD12_PRTCSS PRTCSS Oscillator and PRTCSS Core Supply Voltage 432-MHz devices 1.28 1.35 1.42 V
VDDA12_DAC 1.2-V DAC Supply Voltage 432-MHz devices 1.28 1.35 1.42 V
VPP (5) VPP Supply Voltage 432-MHz devices 1.28 1.35 1.42 V
Supply
Voltage		 VDDS18 1.8-V Supply Voltage 1.71 1.8 1.89 V
VDD18_PRTCSS 1.8-V PWR CTRL Supply Voltage
VDDMXI 1.8-V System Oscillator Supply Voltage
VDD18_DDR 1.8-V DDR2 Supply Voltage
VDDA18_PLL 1.8-V PLL Supply Voltage
VDDA18_USB 1.8-V USB Supply Voltage
VDDA18_VC 1.8-V Voice CODEC Supply Voltage
VDDA18_USB 1.8-V USB Supply Voltage
VDDA18_ADC 1.8-V ADC Supply Voltage
VDDA18_DAC 1.8-V DAC Supply Voltage
VDD_AEMIF1_18_33 1.8/3.3-V switchable EMIF1 Supply Voltage 1.71/3.14 1.8/3.3 1.89/3.46 V
VDD_AEMIF2_18_33 1.8/3.3-V switchable EMIF2 Supply Voltage
VDD_ISIF18_33 1.8/3.3-V switchable ISIF Supply Voltage
VDDS33 3.3-V Supply Voltage 3.14 3.3 3.46 V
VDDA33_USB 3.3-V USB Supply Voltage
VDDA33_VC 3.3-V Voice CODEC Supply Voltage
Supply
Ground		 VSS Core, USB Digital ground
VSS_MX1 OSC (MX1) ground(1)
VSS_32K OSC (32K) ground(1)
VSSA PLL ground(4)
VSSA18_USB USB ground
VSSA33_USB 3.3-V USB ground 0 0 0 V
VSSA33_VC 3.3-V Voice CODEC ground
VSSA18_VC 1.8-V Voice CODEC ground
VSSA_ADC ADC ground
VSSA18_DAC 1.8-V DAC ground
VSSA12_DAC 1.2-V DAC ground
Voltage Input High VIH High-level input voltage(2), excludes switchable I/O
(3.3V I/O)		 2 V
High-level input voltage, non-DDR2 I/O, excludes switchable I/O
(1.8V I/O)		 0.7VDDS18 V
VIH12RTC High-level input voltage I/O (1.35-V)
(PWRCNT/PWRST/RTCXI/RTCXO)		 0.75*VDD12_PRTCSS V
VIH1833 High-level switchable input voltage(2)
(VDD_AEMIF1_18_33, VDD_AEMIF2_18_33, VDD_ISIF_18_33 powered I/Os)(7)(8)(9)(10)		 3.3V I/O mode 2 V
1.8V I/O mode 0.7VDDS18
Voltage Input Low VIL Low-level input voltage(2), excludes switchable I/O
(3.3V I/O)		 0.8 V
Low-level input voltage(2), non-DDR2 I/O, excludes switchable I/O
(1.8V I/O)		 0.3*VDDS18 V
VIL12RTC RTC Low-level input voltage(2)
(1.35V I/O)		 0.25*VDD12_PRTCSS V
VIL1833 Low-level switchable input voltage(2)
(VDD_AEMIF1_18_33, VDD_AEMIF2_18_33, VDD_ISIF_18_33 powered I/Os)		 3.3V I/O mode 0.8 V
1.8V I/O mode 0.3*VDDS18
HD 3CH DAC(3) VREF DAC reference voltage 475 500 525 mV
RBIAS DAC full-scale current adjust resistor 2376 2400 2424 Ω
RLOAD_X Output resistor 74.25 75 75.75 Ω
CBG Bypass capacitor 0.1 uF
Video Buffer(3) ROUT Output resistor (ROUT), between TVOUT and VFB pins 2128.5 2150 2171.5 Ω
RFB Feedback resistor, between VFB and IDACOUT pins. 2079 2100 2121
RBIAS Full-scale current adjust resistor 2400 Ω
CBG Bypass capacitor 0.1 uF
USB USB_VBUS USB external charge pump input 0 5.25 V
VDDA12LDO_USB Internal LDO output(6) 0.22 µF
Voice Codec fs Sampling frequency 8 16 kHz
- System clock 256fs kHz
ADC FSCLK SCLK frequency 2 MHz
Temperature Tc Operating case temperature range Default Temperature 0 85 °C
Extended Temperature [D version devices] –40 85 °C
(1) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground (see Section 7.6.1).
(2) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.
(3) See Section 7.12.2.4. Also, resistors should be E-96 spec line (3 digits with 1% accuracy).
(4) For proper device operation, keep this pin separate from digital ground.
(5) For proper device operation, this pin must always be connected to CVDD.
(6) For proper device operation, this pin must be connected to a 0.22-μF capacitor to VDDA12LDO_USB.
(7) VDD_AEMIF1_18_33: can be used as a power supply for EM_A[3:13], EM_BA0, EM_BA1, EM_CE[0], EM_ADV, EM_CLK, EM_D[8:15 ]pins, Keyscan, or GPIO pins.
(8) VDD_AEMIF2_18_33: can be used as a power supply for EM_A[0:2], EM_CE[1], EM_WE, EM_OE, EM_WAIT, EM_D[0:7] pins, HPI, Keyscan, or GPIO pins.
(9) Example 1: VDD_AEMIF2_18_33 at 1.8-V for 8-bit NAND VDD_AEMIF1_18_33 at 3.3-V for GPIO.
Example 2: VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at 1.8-V for 16-bit NAND.
(10) VDD_ISIF_18_33: can be used as a power supply for VPFE pins (CIN[7:0], YIN[7:0], C_WE_FIELD, PCLK), or SPI3 (SPI3_SCLK,SPI3_SIMO,SPI3_SCS[0], SPI3_SCS[1]) or USBDRVVBUS or GPIO pins.

6.1 Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Case Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS (2) MIN TYP MAX UNIT
Voltage Output(1) VOH High-level output voltage
(3.3V I/O)		 VDDS33 = MIN, IOH = –2mA 2.4 V
High-level output voltage
(3.3V I/O)		 VDDS33 = MIN, IOH = –100μA 2.94
High-level output voltage
(1.8V I/O)		 VDDS18 = MIN, IOH = –2mA VDDS18 - 0.45
VOL Low-level output voltage
(3.3V I/O)		 VDDS33 = MIN, IOL = 2mA 0.4 V
Low-level output voltage
(3.3V I/O)		 VDDS33 = MIN, IOL = 100μA 0.2
Low-level output voltage
(1.8V I/O)		 VDDS18 = MIN, IOH = 2mA 0.45
Current Input/Output II Input current for I/O without
internal pullup/pulldown		 VI = VSS to V DD ±10 μA
II(pullup) Input current for I/O with
internal pullup(3) (4) 		VI = VSS to VDD 100
II(pulldown) Input current for I/O with
internal pulldown(3) (4) 		VI = VSS to VDD –100
IOH High-level output current All peripherals –4000
IOL Low-level output current All peripherals 4000
IOZ (5) I/O off-state output current VO = VDD or VSS
(internal pull disabled)		 ±20
Capacitance CI Input capacitance 4 pF
CO Output capacitance 4
HD 3CH DAC Resolution Resolution 10 Bits
INL Integral non-linearity, best fit RLOAD = 75 Ω
(video buffer disabled)		 –1.5 1.5 LSB
DNL Differential non-linearity RLOAD = 75 Ω
(video buffer disabled)		 –1 1 LSB
VOUT Output compliance range IFS = 6.67 mA, RLOAD = 75 Ω 0 VREF V
ZSET Zero Scale Offset Error 0.5 %
G_ERR Gain Error –5 5 %
Ch_match Channel matching ±2 %
Video Buffer VOH(VIDBUF) Output high voltage
(top of 75% NTSC or PAL colorbar)		 1.35 V
VOL(VIDBUF) Output low voltage
(bottom of sync tip)		 0.35
RES Resolution 10 bits
VOUT Output Voltage RLOAD = 75 Ω 0.35 1.35 V
Voice Codec MIC in to ADC (gain = 20 dB)
Vmic Full scale input 0.063 Vrms
GeAD Gain error 0 dB
Vcom Common voltage 0.9 V
THD + N –1db, 1kHz –62 dB
DNR A-weighted 70 dB
SNR A-weighted 67 dB
Input resistance 10 kΩ
Input capacitance 10 pF
DAC-to-Line Output
Full scale output 0.8 Vrms
Gain error 0 dB
Common voltage 1.5 V
THD + N –60 dB
DNR A-weighted 70 dB
SNR A-weighted 70 dB
Load resistance 10 kΩ
Load capacitance 20 pF
DAC-to-Speaker Output
Output power RL = 8Ω, THD = 10% 240 mW
Output noise A-weighted 120 μVrms
Load resistance 8 Ω
Load capacitance 50 pF
Decimation filter in ADC
Pass band 0.375fs kHz
Pass band ripple ±0.2 dB
Stop band 0.562fs kHz
Stop band attenuation 40 dB
HPF cutoff frequency 1.25mfs Hz
Interpolation filter in DAC
Pass band 0.437fs kHz
Pass band ripple ±0.2 dB
Stop band 0.562fs kHz
Stop band attenuation 40 dB
ADC DNL Static differential non-linearity error FSCLK = 2MHz –1 2.5 LSB
INL Static integral non-linearity error FSCLK = 2MHz –3 3 LSB
ZSET Zero scale offset error –6 6 LSB
FSET Full scale offset error –6 6 LSB
(1) These I/O specifications apply to regular 3.3 V and 1.8V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.
(2) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(3) This specification applies only to pins with an internal pullup (PU) or pulldown (PD). See or Section 3.9 for pin descriptions.
(4) To pull up a signal to the opposite supply rail, a 1-kΩ resistor is recommended.
(5) IOZ applies to output only pins, indicating off-state (Hi-Z) output leakage current.