SPRSP45 March   2020 TMS320F280021 , TMS320F280023 , TMS320F280023C , TMS320F280025 , TMS320F280025C

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 4.4.3 GPIO Input X-BAR
      4. 4.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 4.5 Pins With Internal Pullup and Pulldown
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption
      2. 5.5.1     Operating Mode Test Description
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Design Considerations
    8. 5.8  System
      1. 5.8.1 Power Management
        1. 5.8.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 5.8.1.2 Power Sequencing
        3. 5.8.1.3 Power-On Reset (POR)
        4. 5.8.1.4 Brownout Reset (BOR)
      2. 5.8.2 Reset Timing
        1. 5.8.2.1 Reset Sources
        2. 5.8.2.2 Reset Electrical Data and Timing
          1. Table 5-4 Reset (XRSn) Timing Requirements
          2. Table 5-5 Reset (XRSn) Switching Characteristics
      3. 5.8.3 Clock Specifications
        1. 5.8.3.1 Clock Sources
        2. 5.8.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.8.3.2.1  Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-7  Input Clock Frequency
            2. Table 5-8  XTAL Oscillator Characteristics
            3. Table 5-9  X1 Timing Requirements
            4. Table 5-10 APLL Characteristics
          2. Table 5-11 XCLKOUT Switching Characteristics
          3. Table 5-12 Internal Clock Frequencies
        3. 5.8.3.3 Input Clocks and PLLs
        4. 5.8.3.4 Crystal Oscillator
          1. Table 5-13 Crystal Oscillator Parameters
          2. Table 5-15 Crystal Oscillator Electrical Characteristics
        5. 5.8.3.5 Internal Oscillators
          1. Table 5-16 INTOSC Characteristics
      4. 5.8.4 Flash Parameters
      5. 5.8.5 Emulation/JTAG
        1. 5.8.5.1 JTAG Electrical Data and Timing
          1. Table 5-19 JTAG Timing Requirements
          2. Table 5-20 JTAG Switching Characteristics
        2. 5.8.5.2 cJTAG Electrical Data and Timing
          1. Table 5-21 cJTAG Timing Requirements
          2. Table 5-22 cJTAG Switching Characteristics
      6. 5.8.6 GPIO Electrical Data and Timing
        1. 5.8.6.1 GPIO – Output Timing
          1. Table 5-23 General-Purpose Output Switching Characteristics
        2. 5.8.6.2 GPIO – Input Timing
          1. Table 5-24 General-Purpose Input Timing Requirements
        3. 5.8.6.3 Sampling Window Width for Input Signals
      7. 5.8.7 Interrupts
        1. 5.8.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-25 External Interrupt Timing Requirements
          2. Table 5-26 External Interrupt Switching Characteristics
      8. 5.8.8 Low-Power Modes
        1. 5.8.8.1 Clock-Gating Low-Power Modes
        2. 5.8.8.2 Low-Power Mode Wake-up Timing
          1. Table 5-28 IDLE Mode Timing Requirements
          2. Table 5-29 IDLE Mode Switching Characteristics
          3. Table 5-30 STANDBY Mode Timing Requirements
          4. Table 5-31 STANDBY Mode Switching Characteristics
          5. Table 5-32 HALT Mode Timing Requirements
          6. Table 5-33 HALT Mode Switching Characteristics
    9. 5.9  Analog Peripherals
      1. 5.9.1 Analog-to-Digital Converter (ADC)
        1. 5.9.1.1 ADC Configurability
          1. 5.9.1.1.1 Signal Mode
        2. 5.9.1.2 ADC Electrical Data and Timing
          1. Table 5-37 ADC Operating Conditions
          2. Table 5-38 ADC Characteristics
          3. 5.9.1.2.1  ADC Input Model
          4. 5.9.1.2.2  ADC Timing Diagrams
      2. 5.9.2 Temperature Sensor
        1. 5.9.2.1 Temperature Sensor Electrical Data and Timing
          1. Table 5-43 Temperature Sensor Characteristics
      3. 5.9.3 Comparator Subsystem (CMPSS)
        1. 5.9.3.1 CMPSS Electrical Data and Timing
          1. Table 5-44 Comparator Electrical Characteristics
          2. Table 5-45 CMPSS DAC Static Electrical Characteristics
          3. 5.9.3.1.1  CMPSS Illustrative Graphs
    10. 5.10 Control Peripherals
      1. 5.10.1 Enhanced Pulse Width Modulator (ePWM)
        1. 5.10.1.1 Control Peripherals Synchronization
        2. 5.10.1.2 ePWM Electrical Data and Timing
          1. Table 5-46 ePWM Timing Requirements
          2. Table 5-47 ePWM Switching Characteristics
          3. 5.10.1.2.1 Trip-Zone Input Timing
            1. Table 5-48 Trip-Zone Input Timing Requirements
        3. 5.10.1.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-49 External ADC Start-of-Conversion Switching Characteristics
      2. 5.10.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.10.2.1 HRPWM Electrical Data and Timing
          1. Table 5-50 High-Resolution PWM Characteristics
      3. 5.10.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 5.10.3.1 High-Resolution Capture (HRCAP)
        2. 5.10.3.2 eCAP/HRCAP Synchronization
        3. 5.10.3.3 eCAP Electrical Data and Timing
          1. Table 5-51 eCAP Timing Requirements
          2. Table 5-52 eCAP Switching Characteristics
        4. 5.10.3.4 HRCAP Electrical Data and Timing
          1. Table 5-53 HRCAP Switching Characteristics
      4. 5.10.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.10.4.1 eQEP Electrical Data and Timing
          1. Table 5-54 eQEP Timing Requirements
          2. Table 5-55 eQEP Switching Characteristics
    11. 5.11 Communications Peripherals
      1. 5.11.1 Controller Area Network (CAN)
      2. 5.11.2 Inter-Integrated Circuit (I2C)
        1. 5.11.2.1 I2C Electrical Data and Timing
          1. Table 5-56 I2C Timing Requirements
          2. Table 5-57 I2C Switching Characteristics
      3. 5.11.3 Power Management Bus (PMBus) Interface
        1. 5.11.3.1 PMBus Electrical Data and Timing
          1. Table 5-58 PMBus Electrical Characteristics
          2. Table 5-59 PMBus Fast Mode Switching Characteristics
          3. Table 5-60 PMBus Standard Mode Switching Characteristics
      4. 5.11.4 Serial Communications Interface (SCI)
      5. 5.11.5 Serial Peripheral Interface (SPI)
        1. 5.11.5.1 SPI Master Mode Timings
          1. Table 5-61 SPI Master Mode Timing Requirements
          2. Table 5-62 SPI Master Mode Switching Characteristics (Clock Phase = 0)
          3. Table 5-63 SPI Master Mode Switching Characteristics (Clock Phase = 1)
        2. 5.11.5.2 SPI Slave Mode Timings
          1. Table 5-64 SPI Slave Mode Timing Requirements
          2. Table 5-65 SPI Slave Mode Switching Characteristics
      6. 5.11.6 Local Interconnect Network (LIN)
      7. 5.11.7 Fast Serial Interface (FSI)
        1. 5.11.7.1 FSI Transmitter
          1. 5.11.7.1.1 FSITX Electrical Data and Timing
            1. Table 5-66 FSITX Switching Characteristics
        2. 5.11.7.2 FSI Receiver
          1. 5.11.7.2.1 FSIRX Electrical Data and Timing
            1. Table 5-67 FSIRX Switching Characteristics
            2. Table 5-68 FSIRX Timing Requirements
        3. 5.11.7.3 FSI SPI Compatibility Mode
          1. 5.11.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. Table 5-69 FSITX SPI Signaling Mode Switching Characteristics
      8. 5.11.8 Host Interface Controller (HIC)
        1. 5.11.8.1 HIC Electrical Data and Timing
          1. Table 5-70 HIC Timing Requirements
          2. Table 5-71 HIC Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 Memory Map
        1. 6.3.1.1 Dedicated RAM (Mx RAM)
        2. 6.3.1.2 Local Shared RAM (LSx RAM)
        3. 6.3.1.3 Global Shared RAM (GSx RAM)
      2. 6.3.2 Flash Memory Map
      3. 6.3.3 Peripheral Registers Memory Map
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Floating-Point Unit (FPU)
      2. 6.6.2 Fast Integer Division Unit
      3. 6.6.3 Trigonometric Math Unit (TMU)
      4. 6.6.4 VCRC Unit
    7. 6.7  Embedded Real-Time Analysis and Diagnostic (ERAD)
    8. 6.8  Background CRC-32 (BGCRC)
    9. 6.9  Direct Memory Access (DMA)
    10. 6.10 Device Boot Modes
      1. 6.10.1 Device Boot Configurations
        1. 6.10.1.1 Configuring Boot Mode Pins
        2. 6.10.1.2 Configuring Boot Mode Table Options
      2. 6.10.2 GPIO Assignments
    11. 6.11 Dual Code Security Module
    12. 6.12 Watchdog
    13. 6.13 C28x Timers
    14. 6.14 Dual-Clock Comparator (DCC)
      1. 6.14.1 Features
      2. 6.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
    15. 6.15 Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview