IDLE instruction is executed to
put the device into HALT mode.
The LPM block responds to the
HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being
turned off. This delay enables the CPU pipeline and any other pending operations
to flush properly.
Clocks to the peripherals are
turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is
used as the clock source, the internal oscillator is shut down as well. The
device is now in HALT mode and consumes very little power. It is possible to
keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog
alive in HALT MODE. This is done by writing 1 to CLKSRCCTL1.WDHALTI. After the
IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed
before the wake-up signal could be asserted.
When the GPIOn pin (used to bring
the device out of HALT) is driven low, the oscillator is turned on and the
oscillator wake-up sequence is initiated. The GPIO pin should be driven high
only after the oscillator has stabilized. This enables the provision of a clean
clock signal during the PLL lock sequence. Because the falling edge of the GPIO
pin asynchronously begins the wake-up procedure, care should be taken to
maintain a low noise environment before entering and during HALT mode.
The wake-up signal fed to a GPIO
pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a
GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
When CLKIN to the core is
enabled, the device will respond to the interrupt (if enabled), after some
latency. The HALT mode is now exited.
Normal operation resumes.
The user must relock the PLL upon
HALT wakeup to ensure a stable PLL lock.
Figure 7-28 HALT
Entry and Exit Timing Diagram