The device contains an enhanced capture module (eCAP1). Figure 6-40 shows a functional block diagram of a module.
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.