SPRS439O June   2007  – April 2019 TMS320F28232 , TMS320F28234 , TMS320F28235 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      2. Table 5-2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
      4. 5.5.2     Current Consumption Graphs
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PGF Package
      2. 5.7.2 PTP Package
      3. 5.7.3 ZHH Package
      4. 5.7.4 ZJZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (150-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (100-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7  Input Clock Frequency
        2. Table 5-8  XCLKIN Timing Requirements – PLL Enabled
        3. Table 5-9  XCLKIN Timing Requirements – PLL Disabled
        4. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-11 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-12 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-13 IDLE Mode Timing Requirements
            2. Table 5-14 IDLE Mode Switching Characteristics
            3. Table 5-15 STANDBY Mode Timing Requirements
            4. Table 5-16 STANDBY Mode Switching Characteristics
            5. Table 5-17 HALT Mode Timing Requirements
            6. Table 5-18 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-19 ePWM Timing Requirements
            2. Table 5-20 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-21 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-22 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-23 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-24 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-26 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-27 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-28 External Interrupt Timing Requirements
          2. Table 5-29 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-30 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-31 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-32 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-34 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-35 McBSP Timing Requirements
            2. Table 5-36 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-37 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-38 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-39 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-40 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-41 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-42 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-43 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-44 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the DSP
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-47 External Interface Read Timing Requirements
          2. Table 5-48 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-49 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-50 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-51 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-52 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-53 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-54 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-55 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-56 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-57 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. Table 5-58 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
      7. 5.9.7 Flash Timing
        1. Table 5-59 Flash Endurance for A and S Temperature Material
        2. Table 5-60 Flash Endurance for Q Temperature Material
        3. Table 5-61 Flash Parameters at 150-MHz SYSCLKOUT
        4. Table 5-62 Flash/OTP Access Timing
        5. Table 5-63 Flash Data Retention Duration
    10. 5.10 On-Chip Analog-to-Digital Converter
      1. Table 5-65 ADC Electrical Characteristics (over recommended operating conditions)
      2. 5.10.1     ADC Power-Up Control Bit Timing
        1. Table 5-66 ADC Power-Up Delays
        2. Table 5-67 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 5.10.2     Definitions
      4. 5.10.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-68 Sequential Sampling Mode Timing
      5. 5.10.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-69 Simultaneous Sampling Mode Timing
      6. 5.10.5     Detailed Descriptions
    11. 5.11 Migrating Between F2833x Devices and F2823x Devices
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1–XINT7, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  Analog-to-Digital Converter (ADC) Module
        1. 6.2.7.1 ADC Connections if the ADC Is Not Used
        2. 6.2.7.2 ADC Registers
        3. 6.2.7.3 ADC Calibration
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PGF|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Memory Maps

In Figure 6-23 to Figure 6-25, the following apply:

  • Memory blocks are not to scale.
  • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.
  • Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline order. See the TMS320x2833x, 2823x system control and interrupts reference guide for more details.
  • Certain memory ranges are EALLOW protected against spurious writes after configuration.
  • Locations 0x38 0080–0x38 008F contain the ADC calibration routine. It is not programmable by the user.
  • If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 memmap35_prs439.gifFigure 6-23 F28335, F28333, F28235 Memory Map
TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 memmap_34a_prs439.gifFigure 6-24 F28334, F28234 Memory Map
TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 memmap_32_prs439.gifFigure 6-25 F28332, F28232 Memory Map

Table 6-22 Addresses of Flash Sectors in F28335, F28333, F28235

ADDRESS RANGE PROGRAM AND DATA SPACE
0x30 0000 - 0x30 7FFF Sector H (32K × 16)
0x30 8000 - 0x30 FFFF Sector G (32K × 16)
0x31 0000 - 0x31 7FFF Sector F (32K × 16)
0x31 8000 - 0x31 FFFF Sector E (32K × 16)
0x32 0000 - 0x32 7FFF Sector D (32K × 16)
0x32 8000 - 0x32 FFFF Sector C (32K × 16)
0x33 0000 - 0x33 7FFF Sector B (32K × 16)
0x33 8000 - 0x33 FF7F Sector A (32K × 16)
0x33 FF80 - 0x33 FFF5 Program to 0x0000 when using the
Code Security Module
0x33 FFF6 - 0x33 FFF7 Boot-to-Flash Entry Point
(program branch instruction here)
0x33 FFF8 - 0x33 FFFF Security Password
(128-Bit) (Do Not Program to all zeros)

Table 6-23 Addresses of Flash Sectors in F28334, F28234

ADDRESS RANGE  PROGRAM AND DATA SPACE
0x32 0000 - 0x32 3FFF  Sector H (16K × 16)
0x32 4000 - 0x32 7FFF  Sector G (16K × 16)
0x32 8000 - 0x32 BFFF  Sector F (16K × 16)
0x32 C000 - 0x32 FFFF  Sector E (16K × 16)
0x33 0000 - 0x33 3FFF  Sector D (16K × 16)
0x33 4000 - 0x33 7FFFF  Sector C (16K × 16)
0x33 8000 - 0x33 BFFF  Sector B (16K × 16)
0x33 C000 - 0x33 FF7F  Sector A (16K × 16)
0x33 FF80 - 0x33 FFF5 Program to 0x0000 when using the
Code Security Module
0x33 FFF6 - 0x33 FFF7 Boot-to-Flash Entry Point
(program branch instruction here)
0x33 FFF8 - 0x33 FFFF Security Password (128-Bit)
(Do Not Program to all zeros)

Table 6-24 Addresses of Flash Sectors in F28332, F28232

ADDRESS RANGE  PROGRAM AND DATA SPACE
0x33 0000 - 0x33 3FFF  Sector D (16K × 16)
0x33 4000 - 0x33 7FFFF  Sector C (16K × 16)
0x33 8000 - 0x33 BFFF  Sector B (16K × 16)
0x33 C000 - 0x33 FF7F  Sector A (16K × 16)
0x33 FF80 - 0x33 FFF5 Program to 0x0000 when using the Code Security Module
0x33 FFF6 - 0x33 FFF7 Boot-to-Flash Entry Point (program branch instruction here)
0x33 FFF8 - 0x33 FFFF Security Password (128-Bit) (Do Not Program to all zeros)

NOTE

  • When the code-security passwords are programmed, all addresses from 0x33FF80 to 0x33FFF5 cannot be used as program code or data. These locations must be programmed to 0x0000.
  • If the code security feature is not used, addresses 0x33FF80 to 0x33FFEF may be used for code or data. Addresses 0x33FFF0 to 0x33FFF5 are reserved for data and should not contain program code.

Table 6-25 shows how to handle these memory locations.

Table 6-25 Handling Security Code Locations

ADDRESS FLASH
CODE SECURITY ENABLED CODE SECURITY DISABLED
0x33FF80 – 0x33FFEF Fill with 0x0000 Application code and data
0x33FFF0 – 0x33FFF5 Reserved for data only

Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones.

The wait states for the various spaces in the memory map area are listed in Table 6-26.

Table 6-26 Wait States

AREA WAIT STATES
(CPU)
WAIT STATES
(DMA)(1)
COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait (writes) 0-wait (reads)
1-wait (reads) No access (writes)
Peripheral Frame 3 0-wait (writes) 0-wait (writes) Assumes no conflicts between CPU and DMA.
2-wait (reads) 1-wait (reads)
Peripheral Frame 1 0-wait (writes) No access Cycles can be extended by peripheral generated ready.
2-wait (reads) Consecutive (back-to-back) writes to Peripheral Frame 1 registers will experience a 1-cycle pipeline hit (1-cycle delay)
Peripheral Frame 2 0-wait (writes) No access Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
L0 SARAM 0-wait No access Assumes no CPU conflicts
L1 SARAM
L2 SARAM
L3 SARAM
L4 SARAM 0-wait data (reads) 0-wait Assumes no conflicts between CPU and DMA.
L5 SARAM 0-wait data (writes)
L6 SARAM 1-wait program (reads)
L7 SARAM 1-wait program (writes)
XINTF Programmable Programmable Programmed through the XTIMING registers or extendable through external XREADY signal to meet system timing requirements.
1-wait is minimum wait states allowed on external waveforms for both reads and writes on XINTF.
0-wait minimum writes with write buffer enabled 0-wait minimum writes with write buffer enabled 0-wait minimum for writes assumes write buffer enabled and not full.
Assumes no conflicts between CPU and DMA. When DMA and CPU try simultaneously (conflict), a 1-cycle delay is added for arbitration.
OTP Programmable No access Programmed via the Flash registers.
1-wait minimum 1-wait is minimum number of wait states allowed. 1-wait-state operation is possible at a reduced CPU frequency.
FLASH Programmable No access Programmed via the Flash registers.
1-wait Paged min 0-wait minimum for paged access is not allowed
1-wait Random min
Random ≥ Paged
FLASH Password 16-wait fixed No access Wait states of password locations are fixed.
Boot-ROM 1-wait No access 0-wait speed is not possible.
The DMA has a base of four cycles/word.