Refer to the PDF data sheet for device specific package drawings
|tw(RSL1)(1)||Pulse duration, stable input clock to XRS high||32tc(OSCCLK)||cycles|
|tw(RSL2)||Pulse duration, XRS low||Warm reset||32tc(OSCCLK)||cycles|
|tw(WDRS)||Pulse duration, reset pulse generated by watchdog||512tc(OSCCLK)||cycles|
|td(EX)||Delay time, address/data valid after XRS high||32tc(OSCCLK)||cycles|
|tOSCST(2)||Oscillator start-up time||1||10||ms|
|th(boot-mode)||Hold time for boot-mode pins||200tc(OSCCLK)||cycles|
Figure 5-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating frequency, OSCCLK × 4.