SPRS439Q June   2007  – August 2022 TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      2. 7.5.2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
      4. 7.5.4 Current Consumption Graphs
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PGF Package
      2. 7.7.2 PTP Package
      3. 7.7.3 ZHH Package
      4. 7.7.4 ZAY Package
      5. 7.7.5 ZJZ Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (150-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (100-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset (XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 Input Clock Frequency
        2. 7.9.3.2 XCLKIN Timing Requirements – PLL Enabled
        3. 7.9.3.3 XCLKIN Timing Requirements – PLL Disabled
        4. 7.9.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        5. 7.9.3.5 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements
          2. 7.9.4.3.2 External Interrupt Switching Characteristics
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements
            2. 7.9.4.6.1.2 McBSP Switching Characteristics
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 7.9.5 JTAG Debug Probe Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. 7.9.6.9.2 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
      7. 7.9.7 Flash Timing
        1. 7.9.7.1 Flash Endurance for A and S Temperature Material
        2. 7.9.7.2 Flash Endurance for Q Temperature Material
        3. 7.9.7.3 Flash Parameters at 150-MHz SYSCLKOUT
        4. 7.9.7.4 Flash/OTP Access Timing
        5. 7.9.7.5 Flash Data Retention Duration
    10. 7.10 On-Chip Analog-to-Digital Converter
      1. 7.10.1 ADC Electrical Characteristics (over recommended operating conditions)
      2. 7.10.2 ADC Power-Up Control Bit Timing
        1. 7.10.2.1 ADC Power-Up Delays
        2. 7.10.2.2 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 7.10.3 Definitions
      4. 7.10.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. 7.10.4.1 Sequential Sampling Mode Timing
      5. 7.10.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. 7.10.5.1 Simultaneous Sampling Mode Timing
      6. 7.10.6 Detailed Descriptions
    11. 7.11 Migrating Between F2833x Devices and F2823x Devices
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  Flash
      7. 8.1.7  M0, M1 SARAMs
      8. 8.1.8  L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
      9. 8.1.9  Boot ROM
        1. 8.1.9.1 Peripheral Pins Used by the Bootloader
      10. 8.1.10 Security
      11. 8.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 8.1.12 External Interrupts (XINT1–XINT7, XNMI)
      13. 8.1.13 Oscillator and PLL
      14. 8.1.14 Watchdog
      15. 8.1.15 Peripheral Clocking
      16. 8.1.16 Low-Power Modes
      17. 8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 8.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 8.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 8.1.20 Control Peripherals
      21. 8.1.21 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  Analog-to-Digital Converter (ADC) Module
        1. 8.2.7.1 ADC Connections if the ADC Is Not Used
        2. 8.2.7.2 ADC Registers
        3. 8.2.7.3 ADC Calibration
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Redesign Details
    2. 11.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZJZ|176
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Register Map

The devices contain four peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 8-27.
Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 8-28.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 8-29.
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible peripheral bus. See Table 8-30.
Table 8-27 Peripheral Frame 0 Registers
NAME(1)ADDRESS RANGESIZE (x16)ACCESS TYPE(2)
Device Emulation Registers0x00 0880 – 0x00 09FF384EALLOW protected
FLASH Registers(3)0x00 0A80 – 0x00 0ADF96EALLOW protected
Code Security Module Registers0x00 0AE0 – 0x00 0AEF16EALLOW protected
ADC registers (dual-mapped)
0 wait (DMA), 1 wait (CPU), read only		0x00 0B00 – 0x00 0B0F16Not EALLOW protected
XINTF Registers0x00 0B20 – 0x00 0B3F32EALLOW protected
CPU-Timer 0, CPU-Timer 1, CPU-Timer 2 Registers0x00 0C00 – 0x00 0C3F64Not EALLOW protected
PIE Registers0x00 0CE0 – 0x00 0CFF32Not EALLOW protected
PIE Vector Table0x00 0D00 – 0x00 0DFF256EALLOW protected
DMA Registers0x00 1000 – 0x00 11FF512EALLOW protected
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 8-28 Peripheral Frame 1 Registers
NAMEADDRESS RANGESIZE (x16)
eCAN-A Registers0x00 6000 – 0x00 61FF512
eCAN-B Registers0x00 6200 – 0x00 63FF512
ePWM1 + HRPWM1 Registers0x00 6800 – 0x00 683F64
ePWM2 + HRPWM2 Registers0x00 6840 – 0x00 687F64
ePWM3 + HRPWM3 Registers0x00 6880 – 0x00 68BF64
ePWM4 + HRPWM4 Registers0x00 68C0 – 0x00 68FF64
ePWM5 + HRPWM5 Registers0x00 6900 – 0x00 693F64
ePWM6 + HRPWM6 Registers0x00 6940 – 0x00 697F64
eCAP1 Registers0x00 6A00 – 0x00 6A1F32
eCAP2 Registers0x00 6A20 – 0x00 6A3F32
eCAP3 Registers0x00 6A40 – 0x00 6A5F32
eCAP4 Registers0x00 6A60 – 0x00 6A7F32
eCAP5 Registers0x00 6A80 – 0x00 6A9F32
eCAP6 Registers0x00 6AA0 – 0x00 6ABF32
eQEP1 Registers0x00 6B00 – 0x00 6B3F64
eQEP2 Registers0x00 6B40 – 0x00 6B7F64
GPIO Registers0x00 6F80 – 0x00 6FFF128

 

Table 8-29 Peripheral Frame 2 Registers
NAMEADDRESS RANGESIZE (x16)
System Control Registers0x00 7010 – 0x00 702F32
SPI-A Registers0x00 7040 – 0x00 704F16
SCI-A Registers0x00 7050 – 0x00 705F16
External Interrupt Registers0x00 7070 – 0x00 707F16
ADC Registers0x00 7100 – 0x00 711F32
SCI-B Registers0x00 7750 – 0x00 775F16
SCI-C Registers0x00 7770 – 0x00 777F16
I2C-A Registers0x00 7900 – 0x00 793F64
Table 8-30 Peripheral Frame 3 Registers
NAMEADDRESS RANGESIZE (x16)
McBSP-A Registers (DMA)0x5000 – 0x503F64
McBSP-B Registers (DMA)0x5040 – 0x507F64
ePWM1 + HRPWM1 (DMA)(1)0x5800 – 0x583F64
ePWM2 + HRPWM2 (DMA)0x5840 – 0x587F64
ePWM3 + HRPWM3 (DMA)0x5880 – 0x58BF64
ePWM4 + HRPWM4 (DMA)0x58C0 – 0x58FF64
ePWM5 + HRPWM5 (DMA)0x5900 – 0x593F64
ePWM6 + HRPWM6 (DMA)0x5940 – 0x597F64
(1) The ePWM and HRPWM modules can be re-mapped to Peripheral Frame 3 where they can be accessed by the DMA module. To achieve this, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. This register is EALLOW protected. When this bit is 0, the ePWM and HRPWM modules are mapped to Peripheral Frame 1.