SPRSP14E may   2019  – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pins With Internal Pullup and Pulldown
    5. 6.5 Pin Multiplexing
      1. 6.5.1 GPIO Muxed Pins Table
      2. 6.5.2 Input X-BAR
      3. 6.5.3 Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
      4. 6.5.4 USB Pin Muxing
      5. 6.5.5 High-Speed SPI Pin Muxing
      6. 6.5.6 High-Speed SSI Pin Muxing
    6. 6.6 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
        1. 7.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for ZWT Package
    8. 7.8  Thermal Resistance Characteristics for PTP Package
    9. 7.9  Thermal Design Considerations
    10. 7.10 System
      1. 7.10.1  Power Management Module (PMM)
        1. 7.10.1.1 Introduction
        2. 7.10.1.2 Overview
          1. 7.10.1.2.1 Power Rail Monitors
          2. 7.10.1.2.2 I/O POR (Power-On Reset) Monitor
          3. 7.10.1.2.3 VDD POR (Power-On Reset) Monitor
          4. 7.10.1.2.4 External Supervisor Usage
          5. 7.10.1.2.5 Delay Blocks
        3. 7.10.1.3 External Components
          1. 7.10.1.3.1 Decoupling Capacitors
          2. 7.10.1.3.2 VDDIO Decoupling
        4. 7.10.1.4 Power Sequencing
          1. 7.10.1.4.1 Supply Pins Ganging
          2. 7.10.1.4.2 Signal Pins Power Sequence
          3. 7.10.1.4.3 Supply Pins Power Sequence
            1. 7.10.1.4.3.1 Power Supply Sequence
            2. 7.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 7.10.1.4.3.3 Supply Slew Rate
        5. 7.10.1.5 Power Management Module Electrical Data and Timing
          1. 7.10.1.5.1 Power Management Module Operating Conditions
          2. 7.10.1.5.2 Power Management Module Characteristics
      2. 7.10.2  Reset Timing
        1. 7.10.2.1 Reset Sources
        2. 7.10.2.2 Reset Electrical Data and Timing
          1. 7.10.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.10.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.10.2.2.3 Reset Timing Diagrams
      3. 7.10.3  Clock Specifications
        1. 7.10.3.1 Clock Sources
        2. 7.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.10.3.2.1.1 Input Clock Frequency
            2. 7.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.10.3.2.1.3 X1 Timing Requirements
            4. 7.10.3.2.1.4 AUXCLKIN Timing Requirements
            5. 7.10.3.2.1.5 APLL Characteristics
          2. 7.10.3.2.2 Internal Clock Frequencies
            1. 7.10.3.2.2.1 Internal Clock Frequencies
          3. 7.10.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.10.3.2.3.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 7.10.3.3 Input Clocks
        4. 7.10.3.4 XTAL Oscillator
          1. 7.10.3.4.1 Introduction
          2. 7.10.3.4.2 Overview
            1. 7.10.3.4.2.1 Electrical Oscillator
              1. 7.10.3.4.2.1.1 Modes of Operation
                1. 7.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 7.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 7.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 7.10.3.4.2.2 Quartz Crystal
            3. 7.10.3.4.2.3 GPIO Modes of Operation
          3. 7.10.3.4.3 Functional Operation
            1. 7.10.3.4.3.1 ESR – Effective Series Resistance
            2. 7.10.3.4.3.2 Rneg – Negative Resistance
            3. 7.10.3.4.3.3 Start-up Time
              1. 7.10.3.4.3.3.1 X1/X2 Precondition
            4. 7.10.3.4.3.4 DL – Drive Level
          4. 7.10.3.4.4 How to Choose a Crystal
          5. 7.10.3.4.5 Testing
          6. 7.10.3.4.6 Common Problems and Debug Tips
          7. 7.10.3.4.7 Crystal Oscillator Specifications
            1. 7.10.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 7.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 7.10.3.4.7.3 Crystal Oscillator Parameters
            4. 7.10.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 7.10.3.5 Internal Oscillators
          1. 7.10.3.5.1 INTOSC Characteristics
      4. 7.10.4  Flash Parameters
        1. 7.10.4.1 Flash Parameters 
        2.       111
      5. 7.10.5  RAM Specifications
      6. 7.10.6  ROM Specifications
      7. 7.10.7  Emulation/JTAG
        1. 7.10.7.1 JTAG Electrical Data and Timing
          1. 7.10.7.1.1 JTAG Timing Requirements
          2. 7.10.7.1.2 JTAG Switching Characteristics
          3. 7.10.7.1.3 JTAG Timing
      8. 7.10.8  GPIO Electrical Data and Timing
        1. 7.10.8.1 GPIO - Output Timing
          1. 7.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 7.10.8.1.2 General-Purpose Output Timing
        2. 7.10.8.2 GPIO - Input Timing
          1. 7.10.8.2.1 General-Purpose Input Timing Requirements
          2. 7.10.8.2.2 Sampling Mode
        3. 7.10.8.3 Sampling Window Width for Input Signals
      9. 7.10.9  Interrupts
        1. 7.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.10.9.1.1 External Interrupt Timing Requirements
          2. 7.10.9.1.2 External Interrupt Switching Characteristics
          3. 7.10.9.1.3 External Interrupt Timing
      10. 7.10.10 Low-Power Modes
        1. 7.10.10.1 Clock-Gating Low-Power Modes
        2. 7.10.10.2 Low-Power Mode Wakeup Timing
          1. 7.10.10.2.1 IDLE Mode Timing Requirements
          2. 7.10.10.2.2 IDLE Mode Switching Characteristics
          3. 7.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.10.10.2.4 STANDBY Mode Timing Requirements
          5. 7.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 7.10.10.2.6 STANDBY Entry and Exit Timing Diagram
      11. 7.10.11 External Memory Interface (EMIF)
        1. 7.10.11.1 Asynchronous Memory Support
        2. 7.10.11.2 Synchronous DRAM Support
        3. 7.10.11.3 EMIF Electrical Data and Timing
          1. 7.10.11.3.1 Asynchronous RAM
            1. 7.10.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 7.10.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
            3. 7.10.11.3.1.3 EMIF Asynchronous Memory Timing Diagrams
          2. 7.10.11.3.2 Synchronous RAM
            1. 7.10.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 7.10.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
            3. 7.10.11.3.2.3 EMIF Synchronous Memory Timing Diagrams
    11. 7.11 C28x Analog Peripherals
      1. 7.11.1 Analog Subsystem
      2. 7.11.2 Analog-to-Digital Converter (ADC)
        1. 7.11.2.1 Result Register Mapping
        2. 7.11.2.2 ADC Configurability
          1. 7.11.2.2.1 Signal Mode
        3. 7.11.2.3 ADC Electrical Data and Timing
          1. 7.11.2.3.1 ADC Operating Conditions (16-bit Differential)
            1. 7.11.2.3.1.1 ADC Operating Conditions (16-bit Differential) Notes
          2. 7.11.2.3.2 ADC Characteristics (16-bit Differential)
          3. 7.11.2.3.3 ADC Operating Conditions (16-bit Single-Ended)
            1. 7.11.2.3.3.1 ADC Operating Conditions (16-bit Single-Ended) Notes
          4. 7.11.2.3.4 ADC Characteristics (16-bit Single-Ended)
          5. 7.11.2.3.5 ADC Operating Conditions (12-bit Single-Ended)
            1. 7.11.2.3.5.1 ADC Operating Conditions (12-bit Single-Ended) Notes
          6. 7.11.2.3.6 ADC Characteristics (12-bit Single-Ended)
          7. 7.11.2.3.7 ADCEXTSOC Timing Requirements
          8. 7.11.2.3.8 ADC Input Models
            1. 7.11.2.3.8.1 Single-Ended Input Model Parameters (12-bit Resolution)
            2. 7.11.2.3.8.2 Single-Ended Input Model Parameters (16-bit Resolution)
            3. 7.11.2.3.8.3 Single-Ended Input Model
            4. 7.11.2.3.8.4 Differential Input Model Parameters (16-bit Resolution)
            5. 7.11.2.3.8.5 Differential Input Model
          9. 7.11.2.3.9 ADC Timing Diagrams
            1. 7.11.2.3.9.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 7.11.2.3.9.2 ADC Timings in 16-Bit Mode
        4. 7.11.2.4 Temperature Sensor Electrical Data and Timing
          1. 7.11.2.4.1 Temperature Sensor Characteristics
      3. 7.11.3 Comparator Subsystem (CMPSS)
        1. 7.11.3.1 CMPSS Electrical Data and Timing
          1. 7.11.3.1.1 Comparator Electrical Characteristics
          2. 7.11.3.1.2 CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.11.3.1.3 CMPSS DAC Static Electrical Characteristics
          4. 7.11.3.1.4 CMPSS Illustrative Graphs
          5. 7.11.3.1.5 CMPSS DAC Dynamic Error
      4. 7.11.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.11.4.1 Buffered DAC Electrical Data and Timing
          1. 7.11.4.1.1 Buffered DAC Operating Conditions
          2. 7.11.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.11.4.1.3 Buffered DAC Notes and Illustrative Graphs
    12. 7.12 C28x Control Peripherals
      1. 7.12.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.12.1.1 eCAP Synchronization
        2. 7.12.1.2 eCAP Electrical Data and Timing
          1. 7.12.1.2.1 eCAP Timing Requirements
          2. 7.12.1.2.2 eCAP Switching Charcteristics
        3. 7.12.1.3 HRCAP Electrical Data and Timing
          1. 7.12.1.3.1 HRCAP Switching Characteristics
          2. 7.12.1.3.2 HRCAP Graphs
      2. 7.12.2 Enhanced Pulse Width Modulator (ePWM)
        1. 7.12.2.1 Control Peripherals Synchronization
        2. 7.12.2.2 ePWM Electrical Data and Timing
          1. 7.12.2.2.1 ePWM Timing Requirements
          2. 7.12.2.2.2 ePWM Switching Characteristics
          3. 7.12.2.2.3 Trip-Zone Input Timing
            1. 7.12.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.12.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.12.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 7.12.3 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.12.3.1 HRPWM Electrical Data and Timing
          1. 7.12.3.1.1 High-Resolution PWM Characteristics
      4. 7.12.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.12.4.1 eQEP Electrical Data and Timing
          1. 7.12.4.1.1 eQEP Timing Requirements
          2. 7.12.4.1.2 eQEP Switching Characteristics
      5. 7.12.5 Sigma-Delta Filter Module (SDFM)
        1. 7.12.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 7.12.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.12.5.1.2 SDFM Timing Diagram
    13. 7.13 C28x Communications Peripherals
      1. 7.13.1 Controller Area Network (CAN)
      2. 7.13.2 Fast Serial Interface (FSI)
        1. 7.13.2.1 FSI Transmitter
          1. 7.13.2.1.1 FSITX Electrical Data and Timing
            1. 7.13.2.1.1.1 FSITX Switching Characteristics
            2. 7.13.2.1.1.2 FSITX Timings
        2. 7.13.2.2 FSI Receiver
          1. 7.13.2.2.1 FSIRX Electrical Data and Timing
            1. 7.13.2.2.1.1 FSIRX Timing Requirements
            2. 7.13.2.2.1.2 FSIRX Switching Characteristics
            3. 7.13.2.2.1.3 FSIRX Timing Diagram
        3. 7.13.2.3 SPI Signaling Mode
          1. 7.13.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.13.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.13.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 7.13.3 Inter-Integrated Circuit (I2C)
        1. 7.13.3.1 I2C Electrical Data and Timing
          1. 7.13.3.1.1 I2C Timing Requirements
          2. 7.13.3.1.2 I2C Switching Characteristics
          3. 7.13.3.1.3 I2C Timing Diagram
      4. 7.13.4 Multichannel Buffered Serial Port (McBSP)
        1. 7.13.4.1 McBSP Electrical Data and Timing
          1. 7.13.4.1.1 McBSP Transmit and Receive Timing
            1. 7.13.4.1.1.1 McBSP Timing Requirements
            2. 7.13.4.1.1.2 McBSP Switching Characteristics
            3. 7.13.4.1.1.3 McBSP Receive and Transmit Timing Diagrams
          2. 7.13.4.1.2 McBSP as SPI Master or Slave Timing
            1. 7.13.4.1.2.1 McBSP as SPI Master Timing Requirements
            2. 7.13.4.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 7.13.4.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 7.13.4.1.2.4 McBSP as SPI Slave Switching Characteristics
            5. 7.13.4.1.2.5 McBSP as SPI Master or Slave Timing Diagrams
      5. 7.13.5 Power Management Bus (PMBus)
        1. 7.13.5.1 PMBus Electrical Data and Timing
          1. 7.13.5.1.1 PMBus Electrical Characteristics
          2. 7.13.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.13.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 7.13.6 Serial Communications Interface (SCI)
      7. 7.13.7 Serial Peripheral Interface (SPI)
        1. 7.13.7.1 SPI Electrical Data and Timing
          1. 7.13.7.1.1 SPI Master Mode Timings
            1. 7.13.7.1.1.1 SPI Master Mode Timing Requirements
            2. 7.13.7.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 7.13.7.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            4. 7.13.7.1.1.4 SPI Master Mode External Timing
          2. 7.13.7.1.2 SPI Slave Mode Timings
            1. 7.13.7.1.2.1 SPI Slave Mode Timing Requirements
            2. 7.13.7.1.2.2 SPI Slave Mode Switching Characteristics
            3. 7.13.7.1.2.3 SPI Slave Mode External Timing
      8. 7.13.8 EtherCAT Slave Controller (ESC)
        1. 7.13.8.1 ESC Features
        2. 7.13.8.2 ESC Subsystem Integrated Features
        3. 7.13.8.3 EtherCAT IP Block Diagram
        4. 7.13.8.4 EtherCAT Electrical Data and Timing
          1. 7.13.8.4.1 EtherCAT Timing Requirements
          2. 7.13.8.4.2 EtherCAT Switching Characteristics
          3. 7.13.8.4.3 EtherCAT Timing Diagrams
      9. 7.13.9 Universal Serial Bus (USB) Controller
        1. 7.13.9.1 USB Electrical Data and Timing
          1. 7.13.9.1.1 USB Input Ports DP and DM Timing Requirements
          2. 7.13.9.1.2 USB Output Ports DP and DM Switching Characteristics
    14. 7.14 Connectivity Manager (CM) Peripherals
      1. 7.14.1 Modular Controller Area Network (MCAN) [CAN FD]
      2. 7.14.2 Ethernet Media Access Controller (EMAC)
        1. 7.14.2.1 MAC Features
          1. 7.14.2.1.1 MAC Tx and Rx Features
          2. 7.14.2.1.2 MAC Tx Features
          3. 7.14.2.1.3 MAC Rx Features
        2. 7.14.2.2 Ethernet Electrical Data and Timing
          1. 7.14.2.2.1 Ethernet Timing Requirements
          2. 7.14.2.2.2 Ethernet Switching Characteristics
          3. 7.14.2.2.3 Ethernet Timing Diagrams
        3. 7.14.2.3 Ethernet REVMII Electrical Data and Timing
          1. 7.14.2.3.1 Ethernet REVMII Timing Requirements
          2. 7.14.2.3.2 Ethernet REVMII Switching Characteristics
      3. 7.14.3 Inter-Integrated Circuit (CM-I2C)
        1. 7.14.3.1 CM-I2C Electrical Data and Timing
          1. 7.14.3.1.1 CM-I2C Timing Requirements
          2. 7.14.3.1.2 CM-I2C Switching Characteristics
          3. 7.14.3.1.3 CM-I2C Timing Diagram
      4. 7.14.4 Synchronous Serial Interface (SSI)
        1. 7.14.4.1 SSI Electrical Data and Timing
          1. 7.14.4.1.1 SSI Timing Requirements
          2. 7.14.4.1.2 SSI Characteristics
          3. 7.14.4.1.3 SSI Timing Diagrams
      5. 7.14.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
      6. 7.14.6 Trace Port Interface Unit (TPIU)
        1. 7.14.6.1 TPIU Electrical Data and Timing
          1. 7.14.6.1.1 Trace Port Switching Characteristics
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 C28x Flash Memory Map
      3. 8.3.3 Peripheral Registers Memory Map
      4. 8.3.4 EMIF Chip Select Memory Map
      5. 8.3.5 CM Memory Map
      6. 8.3.6 CM Flash Memory Map
      7. 8.3.7 Peripheral Registers Memory Map (CM)
      8. 8.3.8 Memory Types
        1. 8.3.8.1 Dedicated RAM (Mx and Dx RAM)
        2. 8.3.8.2 Local Shared RAM (LSx RAM)
        3. 8.3.8.3 Global Shared RAM (GSx RAM)
        4. 8.3.8.4 CPU Message RAM (CPU MSGRAM)
        5. 8.3.8.5 CLA Message RAM (CLA MSGRAM)
        6. 8.3.8.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
        7. 8.3.8.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
        8. 8.3.8.8 Dedicated RAM (C0/C1 RAM)
        9. 8.3.8.9 Shared RAM (E0 and Sx RAM)
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  Boot ROM and Peripheral Booting
      1. 8.6.1 Device Boot
      2. 8.6.2 Device Boot Modes
      3. 8.6.3 Device Boot Configurations
      4. 8.6.4 GPIO Assignments for CPU1
    7. 8.7  Dual Code Security Module (DCSM)
    8. 8.8  C28x (CPU1/CPU2) Subsystem
      1. 8.8.1  C28x Processor
        1. 8.8.1.1 Floating-Point Unit
        2. 8.8.1.2 Trigonometric Math Unit
        3. 8.8.1.3 Fast Integer Division Unit
        4. 8.8.1.4 VCRC Unit
      2. 8.8.2  Embedded Real-Time Analysis and Diagnostic (ERAD)
      3. 8.8.3  Background CRC-32 (BGCRC)
      4. 8.8.4  Control Law Accelerator (CLA)
      5. 8.8.5  Direct Memory Access (DMA)
      6. 8.8.6  Interprocessor Communication (IPC) Module
      7. 8.8.7  C28x Timers
      8. 8.8.8  Dual-Clock Comparator (DCC)
        1. 8.8.8.1 Features
        2. 8.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
      9. 8.8.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 8.8.10 Watchdog
      11. 8.8.11 Configurable Logic Block (CLB)
    9. 8.9  Connectivity Manager (CM) Subsystem
      1. 8.9.1  Arm Cortex-M4 Processor
      2. 8.9.2  Nested Vectored Interrupt Controller (NVIC)
      3. 8.9.3  Advance Encryption Standard (AES) Accelerator
      4. 8.9.4  Generic Cyclic Redundancy Check (GCRC) Module
      5. 8.9.5  CM Nonmaskable Interrupt (CMNMI) Module
      6. 8.9.6  Memory Protection Unit (MPU)
      7. 8.9.7  Micro Direct Memory Access (µDMA)
      8. 8.9.8  Watchdog
      9. 8.9.9  CM Clocking
        1. 8.9.9.1 CM Clock Sources
      10. 8.9.10 CM Timers
    10. 8.10 Functional Safety
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application and Implementation
    2. 9.2 Key Device Features
    3. 9.3 Application Information
      1. 9.3.1 Typical Application
        1. 9.3.1.1 High-Voltage Traction Inverter
          1. 9.3.1.1.1 System Block Diagram
          2. 9.3.1.1.2 High-Voltage Traction Inverter Resources
        2. 9.3.1.2 On-Board Charger (OBC)
          1. 9.3.1.2.1 System Block Diagram
          2. 9.3.1.2.2 OBC Resources
        3. 9.3.1.3 Servo Drive Control Module
          1. 9.3.1.3.1 System Block Diagram
          2. 9.3.1.3.2 Servo Drive Control Module Resources
        4. 9.3.1.4 Solar Micro Inverter
          1. 9.3.1.4.1 System Block Diagram
          2. 9.3.1.4.2 Solar Micro Inverter Resources
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Markings
    4. 10.4 Tools and Software
    5. 10.5 Documentation Support
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Peripheral Registers Memory Map

Table 8-3 Peripheral Registers Memory Map
Bit Field Name DriverLib Name Base Address CPU1 CPU2 DMA CLA Pipeline Protected
Instance Structure
Peripheral Frame 0 (PF0)
AdcaResultRegs ADC_RESULT_REGS ADCARESULT_BASE 0x0000_0B00 YES YES YES YES -
AdcbResultRegs ADC_RESULT_REGS ADCBRESULT_BASE 0x0000_0B20 YES YES YES YES -
AdccResultRegs ADC_RESULT_REGS ADCCRESULT_BASE 0x0000_0B40 YES YES YES YES -
AdcdResultRegs ADC_RESULT_REGS ADCDRESULT_BASE 0x0000_0B60 YES YES YES YES -
Peripheral Frame 1 (PF1)
EPwm1Regs EPWM_REGS EPWM1_BASE 0x0000_4000 YES YES YES YES YES
EPwm2Regs EPWM_REGS EPWM2_BASE 0x0000_4100 YES YES YES YES YES
EPwm3Regs EPWM_REGS EPWM3_BASE 0x0000_4200 YES YES YES YES YES
EPwm4Regs EPWM_REGS EPWM4_BASE 0x0000_4300 YES YES YES YES YES
EPwm5Regs EPWM_REGS EPWM5_BASE 0x0000_4400 YES YES YES YES YES
EPwm6Regs EPWM_REGS EPWM6_BASE 0x0000_4500 YES YES YES YES YES
EPwm7Regs EPWM_REGS EPWM7_BASE 0x0000_4600 YES YES YES YES YES
EPwm8Regs EPWM_REGS EPWM8_BASE 0x0000_4700 YES YES YES YES YES
EPwm9Regs EPWM_REGS EPWM9_BASE 0x0000_4800 YES YES YES YES YES
EPwm10Regs EPWM_REGS EPWM10_BASE 0x0000_4900 YES YES YES YES YES
EPwm11Regs EPWM_REGS EPWM11_BASE 0x0000_4A00 YES YES YES YES YES
EPwm12Regs EPWM_REGS EPWM12_BASE 0x0000_4B00 YES YES YES YES YES
EPwm13Regs EPWM_REGS EPWM13_BASE 0x0000_4C00 YES YES YES YES YES
EPwm14Regs EPWM_REGS EPWM14_BASE 0x0000_4D00 YES YES YES YES YES
EPwm15Regs EPWM_REGS EPWM15_BASE 0x0000_4E00 YES YES YES YES YES
EPwm16Regs EPWM_REGS EPWM16_BASE 0x0000_4F00 YES YES YES YES YES
EQep1Regs EQEP_REGS EQEP1_BASE 0x0000_5100 YES YES YES YES YES
EQep2Regs EQEP_REGS EQEP2_BASE 0x0000_5140 YES YES YES YES YES
EQep3Regs EQEP_REGS EQEP3_BASE 0x0000_5180 YES YES YES YES YES
ECap1Regs ECAP_REGS ECAP1_BASE 0x0000_5200 YES YES YES YES YES
ECap2Regs ECAP_REGS ECAP2_BASE 0x0000_5240 YES YES YES YES YES
ECap3Regs ECAP_REGS ECAP3_BASE 0x0000_5280 YES YES YES YES YES
ECap4Regs ECAP_REGS ECAP4_BASE 0x0000_52C0 YES YES YES YES YES
ECap5Regs ECAP_REGS ECAP5_BASE 0x0000_5300 YES YES YES YES YES
ECap6Regs ECAP_REGS ECAP6_BASE 0x0000_5340 YES YES YES YES YES
ECap7Regs ECAP_REGS ECAP7_BASE 0x0000_5380 YES YES YES YES YES
DacaRegs DAC_REGS DACA_BASE 0x0000_5C00 YES YES YES YES YES
DacbRegs DAC_REGS DACB_BASE 0x0000_5C10 YES YES YES YES YES
DaccRegs DAC_REGS DACC_BASE 0x0000_5C20 YES YES YES YES YES
Cmpss1Regs CMPSS_REGS CMPSS1_BASE 0x0000_5C80 YES YES YES YES YES
Cmpss2Regs CMPSS_REGS CMPSS2_BASE 0x0000_5CA0 YES YES YES YES YES
Cmpss3Regs CMPSS_REGS CMPSS3_BASE 0x0000_5CC0 YES YES YES YES YES
Cmpss4Regs CMPSS_REGS CMPSS4_BASE 0x0000_5CE0 YES YES YES YES YES
Cmpss5Regs CMPSS_REGS CMPSS5_BASE 0x0000_5D00 YES YES YES YES YES
Cmpss6Regs CMPSS_REGS CMPSS6_BASE 0x0000_5D20 YES YES YES YES YES
Cmpss7Regs CMPSS_REGS CMPSS7_BASE 0x0000_5D40 YES YES YES YES YES
Cmpss8Regs CMPSS_REGS CMPSS8_BASE 0x0000_5D60 YES YES YES YES YES
Sdfm1Regs SDFM_REGS SDFM1_BASE 0x0000_5E00 YES YES YES YES YES
Sdfm2Regs SDFM_REGS SDFM2_BASE 0x0000_5E80 YES YES YES YES YES
Peripheral Frame 2 (PF2)
SpiaRegs SPI_REGS SPIA_BASE 0x0000_6100 YES YES YES YES YES
SpibRegs SPI_REGS SPIB_BASE 0x0000_6110 YES YES YES YES YES
SpicRegs SPI_REGS SPIC_BASE 0x0000_6120 YES YES YES YES YES
SpidRegs SPI_REGS SPID_BASE 0x0000_6130 YES YES YES YES YES
PmbusaRegs PMBUS_REGS PMBUSA_BASE 0x0000_6400 YES YES YES YES YES
FsiTxaRegs FSI_TX_REGS FSITXA_BASE 0x0000_6600 YES YES YES YES YES
FsiRxaRegs FSI_RX_REGS FSIRXA_BASE 0x0000_6680 YES YES YES YES YES
FsiTxbRegs FSI_TX_REGS FSITXB_BASE 0x0000_6700 YES YES YES YES YES
FsiRxbRegs FSI_RX_REGS FSIRXB_BASE 0x0000_6780 YES YES YES YES YES
FsiRxcRegs FSI_RX_REGS FSIRXC_BASE 0x0000_6880 YES YES YES YES YES
FsiRxdRegs FSI_RX_REGS FSIRXD_BASE 0x0000_6980 YES YES YES YES YES
FsiRxeRegs FSI_RX_REGS FSIRXE_BASE 0x0000_6A80 YES YES YES YES YES
FsiRxfRegs FSI_RX_REGS FSIRXF_BASE 0x0000_6B80 YES YES YES YES YES
FsiRxgRegs FSI_RX_REGS FSIRXG_BASE 0x0000_6C80 YES YES YES YES YES
FsiRxhRegs FSI_RX_REGS FSIRXH_BASE 0x0000_6D80 YES YES YES YES YES
Peripheral Frame 3 (PF3)
AdcaRegs ADC_REGS ADCA_BASE 0x0000_7400 YES YES - YES YES
AdcbRegs ADC_REGS ADCB_BASE 0x0000_7480 YES YES - YES YES
AdccRegs ADC_REGS ADCC_BASE 0x0000_7500 YES YES - YES YES
AdcdRegs ADC_REGS ADCD_BASE 0x0000_7580 YES YES - YES YES
Peripheral Frame 4 (PF4)
InputXbarRegs INPUT_XBAR_REGS INPUTXBAR_BASE 0x0000_7900 YES - - - YES
XbarRegs XBAR_REGS XBAR_BASE 0x0000_7920 YES - - - YES
ClbInputXbarRegs INPUT_XBAR_REGS CLBINPUTXBAR_BASE 0x0000_7960 YES - - - YES
EPwmXbarRegs EPWM_XBAR_REGS EPWMXBAR_BASE 0x0000_7A00 YES - - - YES
CLBXbarRegs CLB_XBAR_REGS CLBXBAR_BASE 0x0000_7A40 YES - - - YES
OutputXbarRegs OUTPUT_XBAR_REGS OUTPUTXBAR_BASE 0x0000_7A80 YES - - - YES
ClbOutputXbarRegs OUTPUT_XBAR_REGS CLBOUTPUTXBAR_BASE 0x0000_7BC0 YES - - - YES
GpioCtrlRegs GPIO_CTRL_REGS GPIOCTRL_BASE 0x0000_7C00 YES - - - YES
Peripheral Frame 5 (PF5)
Emif1ConfigRegs EMIF1_CONFIG_REGS EMIF1CONFIG_BASE 0x0005_F4C0 YES YES - - YES
Peripheral Frame 6 (PF6)
Emif2ConfigRegs EMIF2_CONFIG_REGS EMIF2CONFIG_BASE 0x0005_F4E0 YES - - - YES
Peripheral Frame 9 (PF9)
SciaRegs SCI_REGS SCIA_BASE 0x0000_7200 YES YES - - YES
ScibRegs SCI_REGS SCIB_BASE 0x0000_7210 YES YES - - YES
ScicRegs SCI_REGS SCIC_BASE 0x0000_7220 YES YES - - YES
ScidRegs SCI_REGS SCID_BASE 0x0000_7230 YES YES - - YES
I2caRegs I2C_REGS I2CA_BASE 0x0000_7300 YES YES - - YES
I2cbRegs I2C_REGS I2CB_BASE 0x0000_7340 YES YES - - YES
Peripheral Frame 10 (PF10)
Clb1LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB1_LOGICCFG_BASE 0x0000_3000 YES YES - YES -
Clb1LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB1_LOGICCTL_BASE 0x0000_3100 YES YES - YES -
Clb1DataExchRegs CLB_DATA_EXCHANGE_REGS CLB1_DATAEXCH_BASE 0x0000_3180 YES YES - YES -
Clb2LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB2_LOGICCFG_BASE 0x0000_3200 YES YES - YES -
Clb2LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB2_LOGICCTL_BASE 0x0000_3300 YES YES - YES -
Clb2DataExchRegs CLB_DATA_EXCHANGE_REGS CLB2_DATAEXCH_BASE 0x0000_3380 YES YES - YES -
Clb3LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB3_LOGICCFG_BASE 0x0000_3400 YES YES - YES -
Clb3LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB3_LOGICCTL_BASE 0x0000_3500 YES YES - YES -
Clb3DataExchRegs CLB_DATA_EXCHANGE_REGS CLB3_DATAEXCH_BASE 0x0000_3580 YES YES - YES -
Clb4LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB4_LOGICCFG_BASE 0x0000_3600 YES YES - YES -
Clb4LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB4_LOGICCTL_BASE 0x0000_3700 YES YES - YES -
Clb4DataExchRegs CLB_DATA_EXCHANGE_REGS CLB4_DATAEXCH_BASE 0x0000_3780 YES YES - YES -
Clb5LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB5_LOGICCFG_BASE 0x0000_3800 YES YES - YES -
Clb5LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB5_LOGICCTL_BASE 0x0000_3900 YES YES - YES -
Clb5DataExchRegs CLB_DATA_EXCHANGE_REGS CLB5_DATAEXCH_BASE 0x0000_3980 YES YES - YES -
Clb6LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB6_LOGICCFG_BASE 0x0000_3A00 YES YES - YES -
Clb6LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB6_LOGICCTL_BASE 0x0000_3B00 YES YES - YES -
Clb6DataExchRegs CLB_DATA_EXCHANGE_REGS CLB6_DATAEXCH_BASE 0x0000_3B80 YES YES - YES -
Clb7LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB7_LOGICCFG_BASE 0x0000_3C00 YES YES - YES -
Clb7LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB7_LOGICCTL_BASE 0x0000_3D00 YES YES - YES -
Clb7DataExchRegs CLB_DATA_EXCHANGE_REGS CLB7_DATAEXCH_BASE 0x0000_3D80 YES YES - YES -
Clb8LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB8_LOGICCFG_BASE 0x0000_3E00 YES YES - YES -
Clb8LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB8_LOGICCTL_BASE 0x0000_3F00 YES YES - YES -
Clb8DataExchRegs CLB_DATA_EXCHANGE_REGS CLB8_DATAEXCH_BASE 0x0000_3F80 YES YES - YES -
System Frame
- - M0_RAM_BASE 0x0000_0000 YES YES - - -
- - M1_RAM_BASE 0x0000_0400 YES YES - - -
CpuTimer0Regs CPUTIMER_REGS CPUTIMER0_BASE 0x0000_0C00 YES YES - - -
CpuTimer1Regs CPUTIMER_REGS CPUTIMER1_BASE 0x0000_0C08 YES YES - - -
CpuTimer2Regs CPUTIMER_REGS CPUTIMER2_BASE 0x0000_0C10 YES YES - - -
PieCtrlRegs PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES YES - - -
PieVectTable PIE_VECT_TABLE PIEVECTTABLE_BASE 0x0000_0D00 YES YES - - -
DmaRegs DMA_REGS DMA_BASE 0x0000_1000 YES YES - - -
Dmach1Regs DMA_CH_REGS DMA_CH1_BASE 0x0000_1020 YES YES - - -
Dmach2Regs DMA_CH_REGS DMA_CH2_BASE 0x0000_1040 YES YES - - -
Dmach3Regs DMA_CH_REGS DMA_CH3_BASE 0x0000_1060 YES YES - - -
Dmach4Regs DMA_CH_REGS DMA_CH4_BASE 0x0000_1080 YES YES - - -
Dmach5Regs DMA_CH_REGS DMA_CH5_BASE 0x0000_10A0 YES YES - - -
Dmach6Regs DMA_CH_REGS DMA_CH6_BASE 0x0000_10C0 YES YES - - -
Cla1Regs CLA_REGS CLA1_BASE 0x0000_1400 YES YES - - -
- - CLATOCPU_RAM_BASE 0x0000_1480 YES YES - YES -
- - CPUTOCLA_RAM_BASE 0x0000_1500 YES YES - YES -
- - CLATODMA_RAM_BASE 0x0000_1680 YES YES YES YES -
- - DMATOCLA_RAM_BASE 0x0000_1700 YES YES - YES -
HRCap6Regs HRCAP_REGS HRCAP6_BASE 0x0000_5360 YES YES YES YES YES
HRCap7Regs HRCAP_REGS HRCAP7_BASE 0x0000_53A0 YES YES YES YES YES
McbspaRegs McBSP_REGS MCBSPA_BASE 0x0000_6000 YES YES YES YES YES
McbspbRegs McBSP_REGS MCBSPB_BASE 0x0000_6040 YES YES YES YES YES
BgcrcCpuRegs BGCRC_REGS BGCRC_CPU_BASE 0x0000_6340 YES YES - - YES
BgcrcCla1Regs BGCRC_REGS BGCRC_CLA1_BASE 0x0000_6380 YES YES - YES YES
WdRegs WD_REGS WD_BASE 0x0000_7000 YES YES - - YES
NmiIntruptRegs NMI_INTRUPT_REGS NMI_BASE 0x0000_7060 YES YES - - YES
XintRegs XINT_REGS XINT_BASE 0x0000_7070 YES YES - - YES
SyncSocRegs SYNC_SOC_REGS SYNCSOC_BASE 0x0000_7940 YES - - - YES
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS DMACLASRCSEL_BASE 0x0000_7980 YES YES - - YES
GpioDataRegs GPIO_DATA_REGS GPIODATA_BASE 0x0000_7F00 YES YES - YES YES
GpioDataReadRegs GPIO_DATA_READ_REGS GPIODATAREAD_BASE 0x0000_7F80 YES YES - YES YES
- - LS0_RAM_BASE 0x0000_8000 YES YES - YES -
- - LS1_RAM_BASE 0x0000_8800 YES YES - YES -
- - LS2_RAM_BASE 0x0000_9000 YES YES - YES -
- - LS3_RAM_BASE 0x0000_9800 YES YES - YES -
- - LS4_RAM_BASE 0x0000_A000 YES YES - YES -
- - LS5_RAM_BASE 0x0000_A800 YES YES - YES -
- - LS6_RAM_BASE 0x0000_B000 YES YES - YES -
- - LS7_RAM_BASE 0x0000_B800 YES YES - YES -
- - D0_RAM_BASE 0x0000_C000 YES YES - - -
- - D1_RAM_BASE 0x0000_C800 YES YES YES - -
- - GS0_RAM_BASE 0x0000_D000 YES YES YES - -
- - GS1_RAM_BASE 0x0000_E000 YES YES YES - -
- - GS2_RAM_BASE 0x0000_F000 YES YES YES - -
- - GS3_RAM_BASE 0x0001_0000 YES YES YES - -
- - GS4_RAM_BASE 0x0001_1000 YES YES YES - -
- - GS5_RAM_BASE 0x0001_2000 YES YES YES - -
- - GS6_RAM_BASE 0x0001_3000 YES YES YES - -
- - GS7_RAM_BASE 0x0001_4000 YES YES YES - -
- - GS8_RAM_BASE 0x0001_5000 YES YES YES - -
- - GS9_RAM_BASE 0x0001_6000 YES YES YES - -
- - GS10_RAM_BASE 0x0001_7000 YES YES YES - -
- - GS11_RAM_BASE 0x0001_8000 YES YES YES - -
- - GS12_RAM_BASE 0x0001_9000 YES YES YES - -
- - GS13_RAM_BASE 0x0001_A000 YES YES YES - -
- - GS14_RAM_BASE 0x0001_B000 YES YES YES - -
- - GS15_RAM_BASE 0x0001_C000 YES YES YES - -
- - CMTOCPUXMSGRAM0_BASE 0x0003_8000 YES YES YES - -
- - CMTOCPUXMSGRAM1_BASE 0x0003_8400 YES YES YES - -
- - CPUXTOCMMSGRAM0_BASE 0x0003_9000 YES YES YES - -
- - CPUXTOCMMSGRAM1_BASE 0x0003_9400 YES YES YES - -
- - CPU1TOCPU2MSGRAM0_BASE 0x0003_A000 YES YES YES - -
- - CPU1TOCPU2MSGRAM1_BASE 0x0003_A400 YES YES YES - -
- - CPU2TOCPU1MSGRAM0_BASE 0x0003_B000 YES YES YES - -
- - CPU2TOCPU1MSGRAM1_BASE 0x0003_B400 YES YES YES - -
UsbRegs USB_REGS USBA_BASE 0x0004_0000 YES - YES - YES
Emif1Regs EMIF_REGS EMIF1_BASE 0x0004_7000 YES YES - - YES
Emif2Regs EMIF_REGS EMIF2_BASE 0x0004_7800 YES - - - YES
CanaRegs CAN_REGS CANA_BASE 0x0004_8000 YES YES YES - YES
CanbRegs CAN_REGS CANB_BASE 0x0004_A000 YES YES YES - YES
EscssRegs ESCSS_REGS ESC_SS_BASE 0x0005_7E00 YES - - - YES
EscssConfigRegs ESCSS_CONFIG_REGS ESC_SS_CONFIG_BASE 0x0005_7F00 YES - - - YES
- - MCANA_DRIVER_BASE 0x0005_8000 YES - - - YES
McanaSsRegs MCANSS_REGS MCANASS_BASE 0x0005_C400 YES - - - YES
McanaRegs MCAN_REGS MCANA_BASE 0x0005_C600 YES - - - YES
McanaErrRegs MCAN_ERROR_REGS MCANA_ERROR_BASE 0x0005_C800 YES - - - YES
Cpu2toCpu1IpcRegs CPU1TOCPU2_IPC_REGS_CPU2VIEW - 0x0005_CE00 - YES - - YES
Cpu1toCpu2IpcRegs CPU1TOCPU2_IPC_REGS_CPU1VIEW IPC_CPUXTOCPUX_BASE 0x0005_CE00 YES - - - YES
FlashPumpSemaphoreRegs FLASH_PUMP_SEMAPHORE_REGS FLASHPUMPSEMAPHORE_BASE 0x0005_CE24 YES YES - - YES
Cpu2toCmIpcRegs CPU2TOCM_IPC_REGS_CPU2VIEW - 0x0005_CE40 - YES - - YES
Cpu1toCmIpcRegs CPU1TOCM_IPC_REGS_CPU1VIEW IPC_CPUXTOCM_BASE 0x0005_CE40 YES - - - YES
DevCfgRegs DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - - YES
ClkCfgRegs CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES YES - - YES
CpuSysRegs CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES YES - - YES
SysStatusRegs SYS_STATUS_REGS SYSSTAT_BASE 0x0005_D400 YES YES - - YES
SysPeriphAcRegs CPU2_PERIPH_AC_REGS PERIPHAC_BASE 0x0005_D500 - YES - - YES
SysPeriphAcRegs CPU1_PERIPH_AC_REGS PERIPHAC_BASE 0x0005_D500 YES - - - YES
AnalogSubsysRegs ANALOG_SUBSYS_REGS ANALOGSUBSYS_BASE 0x0005_D700 YES - - - YES
CmConfRegs CM_CONF_REGS CMCONF_BASE 0x0005_DC00 YES - - - YES
HwbistRegs HWBIST_REGS HWBIST_BASE 0x0005_E000 YES YES - - YES
PbistRegs PBIST_REGS PBIST_BASE 0x0005_E200 YES - - - YES
Dcc0Regs DCC_REGS DCC0_BASE 0x0005_E700 YES - - - YES
Dcc1Regs DCC_REGS DCC1_BASE 0x0005_E740 YES - - - YES
Dcc2Regs DCC_REGS DCC2_BASE 0x0005_E780 YES - - - YES
EradGlobalRegs ERAD_GLOBAL_REGS ERAD_GLOBAL_BASE 0x0005_E800 YES YES - - YES
EradHWBP1Regs ERAD_HWBP_REGS ERAD_HWBP1_BASE 0x0005_E900 YES YES - - YES
EradHWBP2Regs ERAD_HWBP_REGS ERAD_HWBP2_BASE 0x0005_E908 YES YES - - YES
EradHWBP3Regs ERAD_HWBP_REGS ERAD_HWBP3_BASE 0x0005_E910 YES YES - - YES
EradHWBP4Regs ERAD_HWBP_REGS ERAD_HWBP4_BASE 0x0005_E918 YES YES - - YES
EradHWBP5Regs ERAD_HWBP_REGS ERAD_HWBP5_BASE 0x0005_E920 YES YES - - YES
EradHWBP6Regs ERAD_HWBP_REGS ERAD_HWBP6_BASE 0x0005_E928 YES YES - - YES
EradHWBP7Regs ERAD_HWBP_REGS ERAD_HWBP7_BASE 0x0005_E930 YES YES - - YES
EradHWBP8Regs ERAD_HWBP_REGS ERAD_HWBP8_BASE 0x0005_E938 YES YES - - YES
EradCounter1Regs ERAD_COUNTER_REGS ERAD_COUNTER1_BASE 0x0005_E980 YES YES - - YES
EradCounter2Regs ERAD_COUNTER_REGS ERAD_COUNTER2_BASE 0x0005_E990 YES YES - - YES
EradCounter3Regs ERAD_COUNTER_REGS ERAD_COUNTER3_BASE 0x0005_E9A0 YES YES - - YES
EradCounter4Regs ERAD_COUNTER_REGS ERAD_COUNTER4_BASE 0x0005_E9B0 YES YES - - YES
EradCRCGlobalRegs ERAD_CRC_GLOBAL_REGS ERAD_CRC_GLOBAL_BASE 0x0005_EA00 YES YES - - YES
EradCRC1Regs ERAD_CRC_REGS ERAD_CRC1_BASE 0x0005_EA10 YES YES - - YES
EradCRC2Regs ERAD_CRC_REGS ERAD_CRC2_BASE 0x0005_EA20 YES YES - - YES
EradCRC3Regs ERAD_CRC_REGS ERAD_CRC3_BASE 0x0005_EA30 YES YES - - YES
EradCRC4Regs ERAD_CRC_REGS ERAD_CRC4_BASE 0x0005_EA40 YES YES - - YES
EradCRC5Regs ERAD_CRC_REGS ERAD_CRC5_BASE 0x0005_EA50 YES YES - - YES
EradCRC6Regs ERAD_CRC_REGS ERAD_CRC6_BASE 0x0005_EA60 YES YES - - YES
EradCRC7Regs ERAD_CRC_REGS ERAD_CRC7_BASE 0x0005_EA70 YES YES - - YES
EradCRC8Regs ERAD_CRC_REGS ERAD_CRC8_BASE 0x0005_EA80 YES YES - - YES
DcsmZ1Regs DCSM_Z1_REGS DCSM_Z1_BASE 0x0005_F000 YES YES - - YES
DcsmZ2Regs DCSM_Z2_REGS DCSM_Z2_BASE 0x0005_F080 YES YES - - YES
DcsmCommonRegs DCSM_COMMON_REGS DCSMCOMMON_BASE 0x0005_F0C0 YES YES - - YES
MemCfgRegs MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES YES - - YES
AccessProtectionRegs ACCESS_PROTECTION_REGS ACCESSPROTECTION_BASE 0x0005_F500 YES YES - - YES
MemoryErrorRegs MEMORY_ERROR_REGS MEMORYERROR_BASE 0x0005_F540 YES YES - - YES
RomWaitStateRegs ROM_WAIT_STATE_REGS ROMWAITSTATE_BASE 0x0005_F580 YES YES - - YES
RomPrefetchRegs ROM_PREFETCH_REGS ROMPREFETCH_BASE 0x0005_F588 YES YES - - YES
TestErrorRegs TEST_ERROR_REGS TESTERROR_BASE 0x0005_F590 YES YES - - YES
Flash0CtrlRegs FLASH_CTRL_REGS FLASH0CTRL_BASE 0x0005_F800 YES YES - - YES
Flash0EccRegs FLASH_ECC_REGS FLASH0ECC_BASE 0x0005_FB00 YES YES - - YES
UidRegs UID_REGS UID_BASE 0x0007_0200 YES YES - - -
CpuIdRegs CPU_ID_REGS CPUID_BASE 0x0007_0223 YES YES - - -
DcsmZ1OtpRegs DCSM_Z1_OTP DCSM_Z1OTP_BASE 0x0007_8000 YES - - - -
DcsmZ2OtpRegs DCSM_Z2_OTP DCSM_Z2OTP_BASE 0x0007_8200 YES - - - -