SCBS881F january   2010  – june 2023 TMS3705

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Characteristics
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings #GUID-D01738F0-6DD5-4A5A-BE33-2BC076228CBE/AMR001
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Electrical Characteristics
    5. 8.5 Thermal Resistance Characteristics for D (SOIC) Package
    6. 8.6 Switching Characteristics
    7. 8.7 Timing Diagrams
  10. 9 Detailed Description
    1. 9.1  Power Supply
    2. 9.2  Oscillator
    3. 9.3  Predrivers
    4. 9.4  Full Bridge
    5. 9.5  RF Amplifier
    6. 9.6  Band-Pass Filter and Limiter
    7. 9.7  Diagnosis
    8. 9.8  Power-on Reset
    9. 9.9  Frequency Divider
    10. 9.10 Digital Demodulator
    11. 9.11 Transponder Resonance-Frequency Measurement
    12. 9.12 SCI Encoder
    13. 9.13 Control Logic
    14. 9.14 Test Pins
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Diagram
  12. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Electrical Characteristics

VDD = 4.5 V to 5.5 V, fosc = 4 MHz, F_SEL = high, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply (VDD, VSS/VSSB, VDDA, VSSA)
IDD Supply current Sum of supply currents in Charge phase, without antenna load 8 20 mA
ISleep Supply current, Sleep state Sum of supply currents in Sleep state, without I/O currents 0.015 0.2 mA
Oscillator (OSC1, OSC2)
gosc Transconductance fosc = 4 MHz, 0.5 Vpp at OSC1 0.5 2 5 mA/V
Cin Input capacitance at OSC1(1) 10 pF
Cout Output capacitance at OSC2(1) 10 pF
Logic Inputs (TXCT, F_SEL, OSC1)
Rpullup Pullup resistance TXCT 120 500 kΩ
F_SEL 10 500
Logic Outputs (SCIO, D_TST)
VOH High-level output voltage 0.8 VDD V
VOL Low-level output voltage 0.2 VDD V
Full-Bridge Outputs (ANT1, ANT2)
ΣRds_on Sum of drain-source resistances Full-bridge N-channel and P-channel MOSFETs at driver current Iant = 50 mA 7 14 Ω
Duty cycle P-channel MOSFETs of full bridge 38% 40% 42%
ton1/ton2 Symmetry of pulse durations for the P‑channel MOSFETs of full bridge 96% 104.5%
Ioc Threshold for overcurrent protection 220 1100 mA
toc Switch-off time of overcurrent protection Short to ground with 3 Ω 0.25 10 µs
tdoc Delay for switching on the full bridge after an overcurrent 2 2.05 2.1 ms
Ileak Leakage current 1 µA
Analog Module (SENSE, SFB, A_TST)
ISENSE Input current SENSE, In charge phase –2 2 mA
VDCREF/ VDD DC reference voltage of RF amplifier, related to VDD 9.25% 10% 11%
GBW Gain-bandwidth product of RF amplifier At 500 kHz with external components to achieve a voltage gain of minimum 4 and 5-mVpp input signal 2 MHz
φO Phase shift of RF amplifier At 134 kHz with external components to achieve a voltage gain of 5 and 20‑mVpp input signal 16 °
Vsfb Peak-to-peak input voltage of band pass at which the limiter comparator should toggle(2) At 134 kHz (corresponds to a minimal total gain of 1000) 5 mV
flow Lower cut-off frequency of band-pass filter(3) 24 60 100 kHz
fhigh Higher cut-off frequency of band-pass filter(3) 160 270 500 kHz
ΔVhys Hysteresis of limiter A_TST pin used as input, D_TST pin as output, offset level determined by band-pass stage 25 50 135 mV
Diagnosis (SENSE)
Idiag Current threshold for operating antenna(4) 80 240 µA
Phase-Locked Loop (D_TST)
fpll PLL frequency 15.984 16 16.0166 MHz
Δf/fpll Jitter of the PLL frequency 6%
Power-On Reset (POR)
Vpor_r POR threshold voltage, rising VDD rising with low slope 1.9 3.5 V
Vpor_f POR threshold voltage, falling VDD falling with low slope 1.3 2.6 V
(1) Specified by design
(2) Specified by design; functional test done for input voltage of 90 mVpp.
(3) Band-pass filter tested at three different frequencies: fmid = 134 kHz and gain > 30 dB; flow = 24 kHz; fhigh = 500 kHz.
Attenuation < –3 dB (reference = measured gain at fmid = 134 kHz).
(4) Internal resistance switched on and much lower than external SENSE resistance.