The control logic is the core of the TMS3705 circuit. This circuit contains a sequencer or a state machine that controls the global operations of the base station (see Figure 9-1). This block has a default mode configuration but can also be controlled by the microcontroller through the TXCT serial input pin to change the configuration and to control the programmable frequency divider. For that purpose a mode control register is implemented in this module that can be written by the microcontroller.

A. In SCI synchronous mode, this transition always occurs approximately 3 ms after leaving Idle state. Diagnostic byte transmission is complete before the transition.

B. A falling edge on TXCT interrupts the receive phase after a delay of 0.9 ms. TXCT must remain low for at least 128 µs. If TXCT is still low after the 0.9-ms delay, the base station enters the Idle state and then the Diagnosis phase one clock cycle later (see the dotted line marked with "See Note C"). No mode control register can be written, and only the default mode is fully supported in this case. Otherwise, if TXCT returns high and remains high during the delay, the base station stays in Idle state and waits for TXCT to go low (which properly starts a new mode control register programming operation) or waits for 100 ms to enter the Sleep state.

C. This transition occurs only in a special case, as described in Note B.

D. A falling edge on TXCT interrupts the Sleep state. Only the default mode is fully supported when starting an operation from the Sleep state with only one falling edge on TXCT, because of the 2-ms delay. For proper mode control register programming, TXCT must return to high and remain high during this delay.

E. Idle state is the next state in case of undefined states (fail-safe state machine).

F. Frequency measurement is available for the TMS3705EDRQ1 and TMS3705FDRQ1 only.

Figure 9-1 Operational State Diagram for the Control Logic

The default mode is a read-only mode that uses the default frequency as the carrier frequency for the full bridge. Therefore the mode control register does not need to be written (it is filled with low states), and the communication sequence between microcontroller and base station starts with TXCT being low for a fixed time to initiate the charge phase. When TXCT becomes high again, the module enters the read phase and the data transmission through the SCIO pin to the microcontroller starts.

There is another read-only mode that differs from the default mode only in the writing of the mode control register before the start of the charge phase. The method to fill the mode control register and the meaning of its contents is described in the following paragraphs.

The write-read mode starts with the programming of the mode control register. Then the charge phase starts with TXCT being low for a fixed time. When TXCT becomes high again, the write phase begins in which the data are transmitted from the microcontroller to the transponder through the TXCT pin, the control logic, the predrivers, and the full bridge by amplitude modulation of 100% with a fixed delay time. After the write phase TXCT goes low again to start another charge or program phase. When TXCT becomes high again, the read phase begins.

The contents of the mode control register (see Table 9-1) define the mode and the way that the carrier frequency generated by the frequency divider is selected to meet the transponder resonance frequency as closely as possible.

The TMS3705EDRQ1 and TMS3705FDRQ1 can adjust the carrier frequency to the transponder resonance frequency automatically by giving the counter state of the transponder resonance-frequency measurement directly to the frequency divider by setting the first 4 bits in high state. The other combinations of the first 4 bits allow the microcontroller to select the default carrier frequency or to use another frequency. The division factor can be selected to be between 114 and 124.

Some bits are included for testability reasons. The default value of these test bits for normal operation is low. Bit 7 (TEST_BIT) is low for normal operation; otherwise, the base station may enter one of the test modes.

The control logic also controls the demodulator, the SCI encoder, the diagnosis, and the transmission of the diagnosis byte during the charge phase.

The state diagram in Figure 9-1 shows the general behavior of the state machine (the state blocks drawn can contain more than one state). All given times are measured from the moment when the state is entered if not specified otherwise.