SPNS141G August   2010  – October 2018 TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS20206 , TMS570LS20216

PRODUCTION DATA.  

  1. 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller
    1. 1.1 Features
    2. 1.2 Description
    3. 1.3 Functional Block Diagram
  2. 2 Device Overview
    1. 2.1 Terms and Acronyms
    2. 2.2 Device Characteristics
    3. 2.3 Memory
      1. 2.3.1 Memory Map
      2. 2.3.2 Flash Memory
      3. 2.3.3 System Modules Assignment
      4. 2.3.4 Peripheral Selects
      5. 2.3.5 Memory Auto-Initialization
      6. 2.3.6 PBIST RAM Self Test
    4. 2.4 Pin Assignments
      1. 2.4.1 PGE QFP Package Pinout (144 pin)
      2. 2.4.2 ZWT BGA Package Pinout (337 ball)
    5. 2.5 Terminal Functions
    6. 2.6 Device Support
      1. 2.6.1 Device and Development-Support Tool Nomenclature
  3. 3 Reset / Abort Sources
    1. 3.1 Reset / Abort Sources
  4. 4 Peripherals
    1. 4.1  Error Signaling Module (ESM)
    2. 4.2  Direct Memory Access (DMA)
    3. 4.3  High End Timer Transfer Unit (HET-TU)
    4. 4.4  Vectored Interrupt Manager (VIM)
    5. 4.5  MIBADC Event Trigger Sources
    6. 4.6  MIBSPI
      1. 4.6.1 MIBSPI Event Trigger Sources
      2. 4.6.2 MIBSPIP5/DMM Pin Multiplexing
    7. 4.7  ETM
    8. 4.8  Debug Scan Chains
      1. 4.8.1 JTAG
    9. 4.9  CCM
      1. 4.9.1 Dual Core Implementation
      2. 4.9.2 CCM-R4
    10. 4.10 LPM
    11. 4.11 Voltage Monitor
    12. 4.12 CRC
    13. 4.13 System Module Access
    14. 4.14 Debug ROM
    15. 4.15 CPU Self Test Controller: STC / LBIST
  5. 5 Device Registers
    1. 5.1 Device Identification Code Register
      1. Table 5-1 Device ID Bit Allocation Register Field Descriptions
    2. 5.2 Die-ID Registers
    3. 5.3 PLL Registers
  6. 6 Device Electrical Specifications
    1. 7 Operating Conditions
      1. 7.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
      2. 7.2 Device Recommended Operating Conditions
      3. 7.3 Electrical Characteristics Over Operating Free-Air Temperature Range
  7. 8 Peripheral and Electrical Specifications
    1. 8.1  Clocks
      1. 8.1.1 PLL And Clock Specifications
      2. 8.1.2 External Reference Resonator/Crystal Oscillator Clock Option
      3. 8.1.3 Validated FMPLL Setting
      4. 8.1.4 LPO And Clock Detection
      5. 8.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks
        1. 8.1.5.1 Timing - Wait States
    2. 8.2  ECLK Specification
      1. 8.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks
    3. 8.3  RST And PORRST Timings
      1. 8.3.1 Timing Requirements For PORRST
      2. 8.3.2 Switching Characteristics Over Recommended Operating Conditions For RST
      3. 8.3.3 IO Status During PORRST
    4. 8.4  TEST Pin Timing
    5. 8.5  DAP - JTAG Scan Interface Timing
      1. 8.5.1 JTAG clock specification 12-MHz and 50-pF load on TDO output
    6. 8.6  Output Timings
      1. 8.6.1 Switching Characteristics For Output Timings Versus Load Capacitance (CL)
    7. 8.7  Input Timings
      1. 8.7.1 Timing Requirements For Input Timings
    8. 8.8  Flash Timings
    9. 8.9  SPI Master Mode Timing Parameters
      1. 8.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
      2. 8.9.2 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
    10. 8.10 SPI Slave Mode Timing Parameters
      1. 8.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)
      2. 8.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)
    11. 8.11 CAN Controller Mode Timings
      1. 8.11.1 Dynamic Characteristics For The CANnTX And CANnRX Pins
    12. 8.12 SCI/LIN Mode Timings
    13. 8.13 FlexRay Controller Mode Timings
      1. 8.13.1 Jitter Timing
    14. 8.14 EMIF Timings
      1. 8.14.1 Read Timing (Asynchronous RAM)
      2. 8.14.2 Write Timing (Asynchronous RAM)
    15. 8.15 ETM Timings
      1. 8.15.1 ETMTRACECLK Timing
      2. 8.15.2 ETMDATA Timing
    16. 8.16 RTP Timings
      1. 8.16.1 RTPCLK Timing
      2. 8.16.2 RTPDATA Timing
      3. 8.16.3 RTPENABLE Timing
    17. 8.17 DMM Timings
      1. 8.17.1 DMMCLK Timing
      2. 8.17.2 DMMDATA Timing
      3. 8.17.3 DMMENA Timing
    18. 8.18 MibADC
      1. 8.18.1 MibADC
      2. 8.18.2 MibADC Recommended Operating Conditions
      3. 8.18.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions
      4. 8.18.4 MibADC Input Model
      5. 8.18.5 MibADC Timings
      6. 8.18.6 MibADC Nonlinearity Error
      7. 8.18.7 MibADC Total Error
  8. 9 Revision History
  9. 10Mechanical Packaging and Orderable Information
    1. 10.1 Thermal Data
      1. 10.1.1 PGE (S-PQFP-G144) plastic Quad Flat Pack
      2. 10.1.2 ZWT (S-PBGA-N337) Plastic ball grid array
    2. 10.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2.3.6 PBIST RAM Self Test

The PBIST (Programmable Built-In Self Test) architecture provides a run-time-programmable memory BIST engine for varying levels of test coverage across the device’s embedded RAM memory. The PBIST architecture consists of a small CPU with an instruction set targeted specifically towards testing RAM memories. This CPU includes both control and instruction registers necessary to execute the individual memory algorithms. In order to minimize test load overhead, once an algorithm is loaded into the instruction registers, it can be run on multiple memories of different sizes or types. The memory configuration information and test algorithm code is stored in an on-chip ROM. The PBIST RAM groups implemented on this device are shown in the following table. More information about memory self test can be found in the PBIST chapter of the device TRM.

Table 2-8 PBIST RAM Grouping

RAM Group Module Memory Type RGS /RDS(1) Test Pattern (Algorithm)
Triple slow read [ROM clock cycles] Triple fast read [ROM clock cycles] March 13N [HCLK/ VCLK(2) cycles] Down 1A [HCLK/ VCLK(2) cycles] Pre-charge [HCLK/ VCLK(2) cycles] Map column [HCLK/ VCLK(2) cycles] DTXN 2A [HCLK/ VCLK(2) cycles] PMOS open [HCLK/ VCLK(2) cycles]
1 PBIST ROM ROM 0/1 12290 4098
2 STC ROM ROM 13/1 24578 8194
3 DCAN1 SP 1/0..2 12600 2637 2064 1914 5490 11544
4 DCAN2 SP 2/0..2 12600 2637 2064 1914 5490 11544
5 DCAN3 SP 3/0..2 6360 1341 1104 1146 2754 5016
6 ESRAM SP, multi-strobe w/page mode 4/21..22 266320 52254 41120 33212 181260 409616
7 MibSPI SP 5/0..5 50160 10458 7968 6900 21924 52272
8 VIM SP 6/0 4200 879 688 638 1830 3848
9 MibADC 2P, sync write async read 7/0..1 8400 1758 1376 1276 3660 7696
10 DMA 2P, sync write async read 8/0..5 18960 4410 3072 2772 6084 Not Available
11 NHET 2P, sync write async read 9/0..11 25440 5940 4224 4008 8136 20064
12 HET TU 2P, sync write async read 10/0..5 6480 1530 1152 1236 2052 4272
13 RTP 2P, sync write async read 11/0..8 37800 8775 6048 5310 12150 34632
14 FlexRay SP 12/0..7 175040 34872 27296 22608 108912 246336
15 ESRAM SP, multi-strobe w/ page mode 4/20 133160 26127 20560 16606 90630 204808
SP = Single Port RAM; 2P = Two Port RAM
(1) RGS (RAM group select) and RDS (return data select) stand for an unique RAM select id. More information about the RGS and the RDS can be found in the technical reference manual (TRM)
(2) The test clock for ESRAM, DMA and RTP is HCLK; the test clock for other modules is VCLK.

NOTE

  • The March13N test algorithm is recommended for application testing.
  • The maximum PBIST test execution speed is limited to 100MHz.
  • The supply current while performing PBIST self test is different than the device operating mode current. These values can be found in the Icc section of the device electrical specifications.