SPNS141G August   2010  – October 2018 TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS20206 , TMS570LS20216

PRODUCTION DATA.  

  1. 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller
    1. 1.1 Features
    2. 1.2 Description
    3. 1.3 Functional Block Diagram
  2. 2 Device Overview
    1. 2.1 Terms and Acronyms
    2. 2.2 Device Characteristics
    3. 2.3 Memory
      1. 2.3.1 Memory Map
      2. 2.3.2 Flash Memory
      3. 2.3.3 System Modules Assignment
      4. 2.3.4 Peripheral Selects
      5. 2.3.5 Memory Auto-Initialization
      6. 2.3.6 PBIST RAM Self Test
    4. 2.4 Pin Assignments
      1. 2.4.1 PGE QFP Package Pinout (144 pin)
      2. 2.4.2 ZWT BGA Package Pinout (337 ball)
    5. 2.5 Terminal Functions
    6. 2.6 Device Support
      1. 2.6.1 Device and Development-Support Tool Nomenclature
  3. 3 Reset / Abort Sources
    1. 3.1 Reset / Abort Sources
  4. 4 Peripherals
    1. 4.1  Error Signaling Module (ESM)
    2. 4.2  Direct Memory Access (DMA)
    3. 4.3  High End Timer Transfer Unit (HET-TU)
    4. 4.4  Vectored Interrupt Manager (VIM)
    5. 4.5  MIBADC Event Trigger Sources
    6. 4.6  MIBSPI
      1. 4.6.1 MIBSPI Event Trigger Sources
      2. 4.6.2 MIBSPIP5/DMM Pin Multiplexing
    7. 4.7  ETM
    8. 4.8  Debug Scan Chains
      1. 4.8.1 JTAG
    9. 4.9  CCM
      1. 4.9.1 Dual Core Implementation
      2. 4.9.2 CCM-R4
    10. 4.10 LPM
    11. 4.11 Voltage Monitor
    12. 4.12 CRC
    13. 4.13 System Module Access
    14. 4.14 Debug ROM
    15. 4.15 CPU Self Test Controller: STC / LBIST
  5. 5 Device Registers
    1. 5.1 Device Identification Code Register
      1. Table 5-1 Device ID Bit Allocation Register Field Descriptions
    2. 5.2 Die-ID Registers
    3. 5.3 PLL Registers
  6. 6 Device Electrical Specifications
    1. 7 Operating Conditions
      1. 7.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
      2. 7.2 Device Recommended Operating Conditions
      3. 7.3 Electrical Characteristics Over Operating Free-Air Temperature Range
  7. 8 Peripheral and Electrical Specifications
    1. 8.1  Clocks
      1. 8.1.1 PLL And Clock Specifications
      2. 8.1.2 External Reference Resonator/Crystal Oscillator Clock Option
      3. 8.1.3 Validated FMPLL Setting
      4. 8.1.4 LPO And Clock Detection
      5. 8.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks
        1. 8.1.5.1 Timing - Wait States
    2. 8.2  ECLK Specification
      1. 8.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks
    3. 8.3  RST And PORRST Timings
      1. 8.3.1 Timing Requirements For PORRST
      2. 8.3.2 Switching Characteristics Over Recommended Operating Conditions For RST
      3. 8.3.3 IO Status During PORRST
    4. 8.4  TEST Pin Timing
    5. 8.5  DAP - JTAG Scan Interface Timing
      1. 8.5.1 JTAG clock specification 12-MHz and 50-pF load on TDO output
    6. 8.6  Output Timings
      1. 8.6.1 Switching Characteristics For Output Timings Versus Load Capacitance (CL)
    7. 8.7  Input Timings
      1. 8.7.1 Timing Requirements For Input Timings
    8. 8.8  Flash Timings
    9. 8.9  SPI Master Mode Timing Parameters
      1. 8.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
      2. 8.9.2 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
    10. 8.10 SPI Slave Mode Timing Parameters
      1. 8.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)
      2. 8.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)
    11. 8.11 CAN Controller Mode Timings
      1. 8.11.1 Dynamic Characteristics For The CANnTX And CANnRX Pins
    12. 8.12 SCI/LIN Mode Timings
    13. 8.13 FlexRay Controller Mode Timings
      1. 8.13.1 Jitter Timing
    14. 8.14 EMIF Timings
      1. 8.14.1 Read Timing (Asynchronous RAM)
      2. 8.14.2 Write Timing (Asynchronous RAM)
    15. 8.15 ETM Timings
      1. 8.15.1 ETMTRACECLK Timing
      2. 8.15.2 ETMDATA Timing
    16. 8.16 RTP Timings
      1. 8.16.1 RTPCLK Timing
      2. 8.16.2 RTPDATA Timing
      3. 8.16.3 RTPENABLE Timing
    17. 8.17 DMM Timings
      1. 8.17.1 DMMCLK Timing
      2. 8.17.2 DMMDATA Timing
      3. 8.17.3 DMMENA Timing
    18. 8.18 MibADC
      1. 8.18.1 MibADC
      2. 8.18.2 MibADC Recommended Operating Conditions
      3. 8.18.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions
      4. 8.18.4 MibADC Input Model
      5. 8.18.5 MibADC Timings
      6. 8.18.6 MibADC Nonlinearity Error
      7. 8.18.7 MibADC Total Error
  8. 9 Revision History
  9. 10Mechanical Packaging and Orderable Information
    1. 10.1 Thermal Data
      1. 10.1.1 PGE (S-PQFP-G144) plastic Quad Flat Pack
      2. 10.1.2 ZWT (S-PBGA-N337) Plastic ball grid array
    2. 10.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3.1 Reset / Abort Sources

The device Resets and Aborts are handled as shown in the following table. The table shows the source of the error, the system mode, the type of error response and the corresponding Error Signaling Module (ESM) channel. Only standard ARM exception handlers and ESM errors are used.

Table 3-1 Reset / Abort Sources

Error Source System Mode Error Response ESM Hookup group channel
1) CPU transactions
Precise write error (Strongly Ordered) User/Privilege Precise Abort (CPU) n/a
Precise read error (Device or Normal) User/Privilege Precise Abort (CPU) n/a
Imprecise write error (Device or Normal) User/Privilege Imprecise Abort (CPU) n/a
Illegal instruction User/Privilege Undefined Instruction Trap (CPU)(1) n/a
MPU access violation User/Privilege Abort (CPU) n/a
2) SRAM
B0 Tightly Coupled Memory (TCM) (even) ECC single error (correctable) User/Privilege ESM 1.26
B0 TCM (even) ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.3
B0 TCM (even) uncorrectable error (i.e. redundant address decode) User/Privilege ESM => NMI 2.6
B0 TCM (even) address bus parity error User/Privilege ESM => NMI 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
B1 TCM (odd) ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.5
B1 TCM (odd) uncorrectable error (i.e. redundant address decode) User/Privilege ESM => NMI 2.8
B1 TCM (odd) address bus parity error User/Privilege ESM => NMI 2.12
3) Flash with ECC INTEGRATED INTO CPU
ECC single error (correctable) User/Privilege ESM 1.6
ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.7
Uncorrectable error (i.e. redundant address tag, redundant syndrome compare, address bus parity, etc.) User/Privilege ESM => NMI 2.4
4) DMA transactions
External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13
Memory access permission violation User/Privilege ESM 1.2
Memory parity error User/Privilege ESM 1.3
5) DMM transactions
External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13
6) AHB-AP transactions
External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13
7) HET TU
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
8) NHET
Memory parity error User/Privilege ESM 1.7
9) MibSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MibSPI3 memory parity error User/Privilege ESM 1.18
MibSPIP5 memory parity error User/Privilege ESM 1.24
10) MibADC
MibADC1 memory parity error User/Privilege ESM 1.19
MibADC2 memory parity error User/Privilege ESM 1.1
11) DCAN
DCAN1 memory parity error User/Privilege ESM 1.21
DCAN2 memory parity error User/Privilege ESM 1.23
DCAN3 memory parity error User/Privilege ESM 1.22
12) PLL
PLL slip error User/Privilege ESM 1.10
13) Clock monitor
Clock monitor interrupt User/Privilege ESM 1.11
14) CCM
Self test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM => NMI 2.2
15) FlexRay
Memory parity error User/Privilege ESM 1.12
16) FlexRay TU
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.16
Memory parity error User/Privilege ESM 1.14
17) VIM
Memory parity error User/Privilege ESM 1.15
18) voltage monitor
VMON out of voltage range n/a Reset n/a
19) CPU Selftest (LBIST)
CPU Selftest (LBIST) error User/Privilege ESM 1.27
20) errors reflected in the SYSESR register
Power-Up Reset; VCC out of voltage range n/a Reset n/a
Oscillator fail / PLL slip(2) n/a Reset n/a
Watchdog time limit exceeded n/a Reset n/a
CPU Reset n/a Reset n/a
Software Reset n/a Reset n/a
External Reset n/a Reset n/a
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the Code reaches the execute stage of the CPU.
(2) Oscillator fail/PLL slip can be configured in the system register PLLCTL1 to generate a reset.