SPNS230D October   2013  – February 2015 TMS570LS3137-EP

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison Table
    1. 3.1 Device Comparison
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Diagrams
      1. 4.1.1 Pin Attributes
        1. 4.1.1.1 GWT Package
          1. 4.1.1.1.1  Multi-Buffered Analog-to-Digital Converters (MibADC)
          2. 4.1.1.1.2  Enhanced High-End Timer Modules (N2HET)
          3. 4.1.1.1.3  General-Purpose Input / Output (GPIO)
          4. 4.1.1.1.4  FlexRay Interface Controller (FlexRay)
          5. 4.1.1.1.5  Controller Area Network Controllers (DCAN)
          6. 4.1.1.1.6  Local Interconnect Network Interface Module (LIN)
          7. 4.1.1.1.7  Standard Serial Communication Interface (SCI)
          8. 4.1.1.1.8  Inter-Integrated Circuit Interface Module (I2C)
          9. 4.1.1.1.9  Standard Serial Peripheral Interface (SPI)
          10. 4.1.1.1.10 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
          11. 4.1.1.1.11 Ethernet Controller
          12. 4.1.1.1.12 External Memory Interface (EMIF)
          13. 4.1.1.1.13 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
          14. 4.1.1.1.14 RAM Trace Port (RTP)
          15. 4.1.1.1.15 Data Modification Module (DMM)
          16. 4.1.1.1.16 System Module Interface
          17. 4.1.1.1.17 Clock Inputs and Outputs
          18. 4.1.1.1.18 Test and Debug Modules Interface
          19. 4.1.1.1.19 Flash Supply and Test Pads
          20. 4.1.1.1.20 No Connects
          21. 4.1.1.1.21 Supply for Core Logic: 1.2V nominal
          22. 4.1.1.1.22 Supply for I/O Cells: 3.3V nominal
          23. 4.1.1.1.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption
    6. 5.6  Thermal Data
    7. 5.7  Switching Characteristics
    8. 5.8  Wait States Required
    9. 5.9  I/O Electrical Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM© Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator (LPO)
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Master/Slave Access Privileges
        1. 6.9.3.1 Special Notes on Accesses to Certain Slaves
      4. 6.9.4 POM Overlay Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings for Program Flash
      6. 6.10.6 Flash Program and Erase Timings for Data Flash
    11. 6.11 Tightly-Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAMW ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1  Block Diagram
      2. 6.21.2  Debug Components Memory Map
      3. 6.21.3  JTAG Identification Code
      4. 6.21.4  Debug ROM
      5. 6.21.5  JTAG Scan Interface Timings
      6. 6.21.6  Advanced JTAG Security Module
      7. 6.21.7  Embedded Trace Macrocell (ETM-R4)
        1. 6.21.7.1 ETM TRACECLKIN Selection
        2. 6.21.7.2 Timing Specifications
      8. 6.21.8  RAM Trace Port (RTP)
        1. 6.21.8.1 Features
        2. 6.21.8.2 Timing Specifications
      9. 6.21.9  Data Modification Module (DMM)
        1. 6.21.9.1 Features
        2. 6.21.9.2 Timing Specifications
      10. 6.21.10 Boundary Scan Chain
  7. 7Peripheral Information
    1. 7.1  Peripheral Legend
    2. 7.2  Multi-Buffered 12bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 Default MIBADC1 Event Trigger Hookup
        2. 7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
        3. 7.2.2.3 Default MIBADC2 Event Trigger Hookup
        4. 7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3  General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4  Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET1-N2HET2 Interconnections
      5. 7.4.5 N2HET Checking
        1. 7.4.5.1 Internal Monitoring
        2. 7.4.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.4.6 Disabling N2HET Outputs
      7. 7.4.7 High-End Timer Transfer Unit (HET-TU)
        1. 7.4.7.1 Features
        2. 7.4.7.2 Trigger Connections
    5. 7.5  FlexRay Interface
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
      3. 7.5.3 FlexRay Transfer Unit
    6. 7.6  Controller Area Network (DCAN)
      1. 7.6.1 Features
      2. 7.6.2 Electrical and Timing Specifications
    7. 7.7  Local Interconnect Network Interface (LIN)
      1. 7.7.1 LIN Features
    8. 7.8  Serial Communication Interface (SCI)
      1. 7.8.1 Features
    9. 7.9  Inter-Integrated Circuit (I2C)
      1. 7.9.1 Features
      2. 7.9.2 I2C I/O Timing Specifications
    10. 7.10 Multi-Buffered / Standard Serial Peripheral Interface
      1. 7.10.1 Features
      2. 7.10.2 MibSPI Transmit and Receive RAM Organization
      3. 7.10.3 MibSPI Transmit Trigger Events
        1. 7.10.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.10.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.10.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.10.5 SPI Slave Mode I/O Timings
    11. 7.11 Ethernet Media Access Controller
      1. 7.11.1 Ethernet MII Electrical and Timing Specifications
      2. 7.11.2 Ethernet RMII Timing
      3. 7.11.3 Management Data Input/Output (MDIO)
  8. 8Device and Documentation Support
    1. 8.1 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Device and Documentation Support

8.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (for example, TMS570LS3137). These prefixes represent evolutionary stages of product development from engineering prototypes (TMX) through fully qualified production devices/tools (TMS).

Device development evolutionary flow:

    TMX Experimental device that is not necessarily representative of the final device's electrical specifications.
    TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification.
    TMS Fully-qualified production device.

TMX and TMP devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TMS570LS3137-EP device_numbering_conv_f14_spns230.gifFigure 8-1 TMS570LS3137-EP Device Numbering Conventions

8.2 Documentation Support

8.2.1 Related Documentation from Texas Instruments

The following documents describe the TMS570LS3137-EP microcontroller.

SPNU499 TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsytem in the device.
SPNZ195 TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision C) describes the known exceptions to the functional specifications for the device silicon revision(s).

8.2.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

8.3 Trademarks

E2E is a trademark of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM is a registered trademark of ARM Limited.

All other trademarks are the property of their respective owners.

8.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

8.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

8.6 Device Identification

8.6.1 Device Identification Code Register

The device identification code register identifies several aspects of the device including the silicon version. The details of the device identification code register are shown in Table 8-1. The device identification code register value for this device is:

  • Rev A = 0x802AAD05
  • Rev B = 0x802AAD15
  • Rev C = 0x802AAD1D

Figure 8-2 Device ID Bit Allocation Register
31 30 29 28 27 26 25 24
CP-15 UNIQUE ID
R-1 R-0000000
23 22 21 20 19 18 17 16
UNIQUE ID TECH
R-0010101 R-0
15 14 13 12 11 10 9 8
TECH I/O VOLTAGE PERIPH PARITY FLASH ECC RAM ECC
R-101 R-0 R-1 R-10 R-1
7 6 5 4 3 2 1 0
VERSION 1 0 1
R-00000 R-1 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-1 Device ID Bit Allocation Register Field Descriptions

Bit Field Value Description
31 CP15 Indicates the presence of coprocessor 15
1 CP15 present
30-17 UNIQUE ID 10101

Silicon version (revision) bits.

This bitfield holds a unique number for a dedicated device configuration (die).
16-13 TECH Process technology on which the device is manufactured.
0101 F021
12 I/O VOLTAGE I/O voltage of the device.
0 I/O are 3.3v
11 PERIPHERAL PARITY Peripheral Parity
1 Parity on peripheral memories
10-9 FLASH ECC Flash ECC
10 Program memory with ECC
8 RAM ECC Indicates if RAM memory ECC is present.
1 ECC implemented
7-3 REVISION Revision of the Device.
2-0 101 The platform family ID is always 0b101

8.6.2 Die Identification Registers

The four die ID registers at addresses 0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a 128-bit dieid with the information as shown in Table 8-2.

Table 8-2 Die-ID Registers

Item Number of Bits Bit Location
X-coordinate on wafer 12 0xFFFFE1F0[11:0]
Y-coordinate on wafer 12 0xFFFFE1F0[23:12]
Wafer number 8 0xFFFFE1F0[31:24]
Lot number 24 0xFFFFE1F4[23:0]
Reserved 72 0xFFFFE1F4[31:24], 0xFFFFE1F8[31:0], 0xFFFFE1FC[31:0]

8.7 Module Certifications

The following communications modules have received certification of adherence to a standard.

FlexRay™ Certifications

TMS570LS3137-EP FlexRay_Certification_TMS570LS3137ZWT_RevC_2013-04-27.gifFigure 8-3 Flexray Certification for GWT Package

DCAN Certification

TMS570LS3137-EP CAN_Certification_2011_02_08.pngFigure 8-4 DCAN Certification