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Enhanced Product 16/32 Bit RISC Flash Arm Cortex-R4F, EMAC, FlexRay

TMS570LS3137-EP

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Product details

Parameters

CPU Arm-Cortex - R4F Frequency (MHz) 180 Operating temperature range (C) -40 to 125, -55 to 125 Flash (KB) 3072 RAM (KB) 256 Data flash (KB) 64 Ethernet MAC 10/100 FlexRay 2-ch ADC 2 x 12-Bit (24ch) CAN (#) 3 PWM (Ch) 0 HET channels 44 MibSPI 3 SPI 2 SCI/LIN 2/1 I2C 1 UART (SCI) 2 GPIO 144 EMIF 16-bit open-in-new Find other Hercules MCUs for functional safety

Package | Pins | Size

NFBGA (GWT) 337 256 mm² 16 x 16 open-in-new Find other Hercules MCUs for functional safety

Features

  • High-Performance Microcontroller for Safety-
    Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM interfaces
    • Built-In Self-Test for CPU and On-chip RAMs
    • Error Signaling Module with Error Pin
    • Voltage and Clock Monitoring
  • ARM® Cortex – R4F 32-Bit RISC CPU
    • Efficient 1.66 DMIPS/MHz with 8-Stage Pipeline
    • FPU with Single- and Double-Precision
    • 12-Region Memory Protection Unit
    • Open Architecture with Third-Party Support
  • Operating Conditions
    • Up to 180-MHz System Clock
    • Core Supply Voltage (VCC): 1.2 V Nominal
    • I/O Supply Voltage (VCCIO): 3.3 V Nominal
    • ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
    • IP Modules GBD for –40°C to 125°C Only
      includes Flash, MibADC timings, nPORRST,
      N2HET, and FlexRay
  • Integrated Memory
    • 3MB of Program Flash With ECC
    • 256KB of RAM With ECC
    • 64KB of Flash With ECC for Emulated
      EEPROM
  • 16-Bit External Memory Interface
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt Timer (RTI) OS Timer
    • 96-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Control Packets
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked-Loop
    (FMPLL) with Built-In Slip Detector
  • Separate Nonmodulating PLL
  • IEEE 1149.1 JTAG, Boundary Scan and ARM
    CoreSight™ Components
  • JTAG Security Module
  • Trace and Calibration Capabilities
    • Embedded Trace Macrocell (ETM-R4)
    • Data Modification Module (DMM)
    • RAM Trace Port (RTP)
    • Parameter Overlay Module (POM)
  • Multiple Communication Interfaces
    • 10/100 Mbps Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant (3.3-V I/O only)
      • Supports MII, RMII and MDIO
    • FlexRay Controller with Two Channels
      • 8 KB message RAM with Parity Protection
      • Dedicated Transfer Unit (FTU)
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes, Each with Parity Protection
      • Compliant to CAN Protocol Version 2.0B
    • Local Interconnect Network (LIN) Interface
      Controller
      • Compliant to LIN Protocol Version 2.1
      • Can be Configured as a Second SCI
    • Standard Serial Communication Interface (SCI)
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interfaces
      (MibSPIs)
      • 128 Words with Parity Protection Each
    • Two Standard Serial Peripheral Interfaces
      (SPIs)
  • Two High-End Timer Modules (N2HETs)
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM with Parity Protection
      Each
    • Each N2HET Includes Hardware Angle
      Generator
    • Dedicated Transfer Unit with MPU for Each
      N2HET (HTU)
  • Two 10- or 12-bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared with ADC1
    • 64 Result Buffers with Parity Protection Each
  • Sixteen General-Purpose Input/Output Pins (GPIO)
    Capable of Generating Interrupts
  • Package
    • 337-Ball Grid Array (SnPb) (GWT)
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Description

The TMS570LS3137-EP device is a high-performance microcontroller family for safety systems. The safety architecture includes the following:

  • Dual CPUs in lockstep
  • CPU and memory built-in self-test (BIST) logic
  • ECC on both the flash and the data SRAM
  • Parity on peripheral memories
  • Loopback capability on peripheral I/Os

The TMS570LS3137-EP device integrates the ARM Cortex-R4F Floating-Point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.

The TMS570LS3137-EP device has 3MB of integrated flash and 256KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word and double-word modes.

The TMS570LS3137-EP device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit analog-to-digital converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode.

The device has multiple communication interfaces: three MibSPIs, , one LIN, one SCI, three DCANs, one I2C. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.

The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the global clock module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The DMA controller has 16 channels, 32 control packets and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals or FPGA devices.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built in ARM Cortex-R4F CoreSight debug features an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows parameters and tables to be dynamically calibrated against production code without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.

With integrated safety features and a wide choice of communication and control peripherals, the device is an ideal solution for high-performance real-time control applications with safety-critical requirements.

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Technical documentation

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No results found. Please clear your search and try again. View all 37
Type Title Date
* Datasheet TMS570LS3137-EP 16- and 32-Bit RISC Flash Microcontroller datasheet (Rev. D) Feb. 20, 2015
* Errata TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision C) (Rev. G) May 31, 2016
* Errata TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision D) (Rev. B) May 31, 2016
* User guides TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (Rev. C) Mar. 01, 2018
* Radiation & Reliability reports TMS5703137CGWTMEP Reliability Report Feb. 06, 2015
* Radiation & Reliability reports TMS5703137CGWTQEP Reliability Report Dec. 22, 2014
More literature Hercules™ Diagnostic Library Test Automation Unit User Guide (Rev. B) Jan. 09, 2020
More literature HALCoGen-CSP 04.07.01 (Rev. C) Jan. 08, 2020
User guides HALCoGen-CSP Installation Guide (Rev. B) Jan. 08, 2020
User guides HALCoGen-CSP User's Guide (Rev. C) Jan. 08, 2020
User guides Hercules Diagnostic Library -TAU Installation Guide (Rev. B) Jan. 08, 2020
User guides Hercules Diagnostic Library CSP Without LDRA Oct. 29, 2019
Selection guides Enhanced Product Selection Guide (Rev. B) Oct. 11, 2019
Application notes HALCoGen Ethernet Driver With lwIP Integration Demo and Active Webserver Demo Sep. 13, 2019
Application notes CAN Bus Bootloader for Hercules Microcontrollers Aug. 21, 2019
Application notes HALCoGen CSP Without LDRA Release_Notes Aug. 19, 2019
User guides HALCoGen-CSP Without LDRA Installation Guide Aug. 19, 2019
User guides HALCoGen-CSP Without LDRA User's Guide Aug. 19, 2019
User guides Hercules Diagnostic Library - Without LDRA Installation Guide Aug. 19, 2019
User guides Hercules™ Diag Lib Test Automation Unit Without LDRA User's Guide Aug. 19, 2019
Application notes Sharing FEE Blocks Between the Bootloader and the Application Nov. 07, 2017
Application notes Sharing Exception Vectors on Hercules™ Based Microcontrollers Mar. 27, 2017
Application notes How to Create a HALCoGen Based Project For CCS (Rev. B) Aug. 09, 2016
Application notes Using the CRC Module on Hercules™-Based Microcontrollers Aug. 04, 2016
Application notes Using the SPI as an Extra UART Transmitter Jul. 26, 2016
VID TMS570LS3137-EP VID V6213629 Jun. 21, 2016
Application notes High Speed Serial Bus Using the MibSPIP Module on Hercules-Based MCUs Apr. 22, 2016
Application notes Triggering ADC Using Internal Timer Events on Hercules MCUs Oct. 19, 2015
Application notes Continuous Monitor of the PLL Frequency With the DCC Jul. 24, 2015
Technical articles How fast is your 32-bit MCU? Jul. 15, 2015
Technical articles Easily increase functionality in motor drive applications May 19, 2015
White papers Foundational Software for Functional Safety May 12, 2015
Application notes Sine Wave Generation Using PWM With Hercules N2HET and HTU May 12, 2015
Application notes Triangle/Trapezoid Wave Generation Using PWM With Hercules N2HET May 01, 2015
Technical articles Really smart cities in real time Apr. 25, 2015
Application notes Hercules SCI With DMA Mar. 22, 2015
Technical articles How to have it all: Designing next-generation industrial drive and control systems Apr. 03, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

DEVELOPMENT KITS Download
document-generic User guide
199
Description

The TMS570LS31 Hercules™ Development Kit is based on the IEC 61508 SIL 3 and ISO 26262 ASIL D certified TMS570LS3137 and is ideal for getting started on development with TMS570LS31x/21x series of the Hercules TMS570 microcontroller family. The development board features RJ45 10/100 Ethernet, two CAN (...)

Features
  • On-board USB XDS100v2 JTAG debug
  • On-board SCI-to-PC serial communication
  • External high-speed emulation via JTAG
  • Access to signal pin test points
  • LEDs, temp sensor and light sensor
  • CAN transceivers
  • MIPI connector for 32bit ETM Trace
  • RJ-45 10/100 Ethernet interface

Software development

DEBUG PROBES Download
XDS100v2 JTAG Debug Probe (14-pin TI version)
TMDSEMU100V2U-14T — The Spectrum Digital XDS100v2 is the second generation of the XDS100 family of debug probes (emulators) for TI processors. The XDS100 family features the lowest cost of all the XDS family of debug probes while supporting the traditional JTAG standard (IEEE1149.1). Also, all XDS debug probes support (...)
Features

The XDS100v2 is the second generation of the XDS100 family of low cost JTAG debug probes (emulators) for TI processors. Designed to deliver full featured JTAG connectivity at a low cost, the XDS100 is the family of choice for entry-level debugging of TI microcontrollers, processors and wireless (...)

DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
295
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

995
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

1495
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Hercules Safety MCUs
CCSTUDIO-SAFETY

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

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Package Pins Download
NFBGA (GWT) 337 View options

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