SCDS473 July   2025 TMUX9612

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings: TMUX961x Devices
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions: TMUX961x Devices
    4. 6.4  Source and Drain Continuous Current
    5. 6.5  Source and Drain Pulse Current
    6. 6.6  Electrical Characteristics (Global): TMUX961x Devices
    7. 6.7  Electrical Characteristics (±110V Dual Supply)
    8. 6.8  Electrical Characteristics (±50V Dual Supply)
    9. 6.9  Electrical Characteristics (100V Single Supply)
    10. 6.10 Switching Characteristics: TMUX961x Devices
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 On-Resistance
    2. 7.2 Off-Leakage Current
    3. 7.3 On-Leakage Current
    4. 7.4 Device Turn-On and Turn-Off Time
    5. 7.5 Charge Injection
    6. 7.6 Off Isolation
    7. 7.7 Crosstalk
    8. 7.8 Bandwidth
    9. 7.9 THD + Noise
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Flat On-Resistance
      3. 8.3.3 Protection Features
        1. 8.3.3.1 Fail-Safe Logic
        2. 8.3.3.2 ESD Protection
        3. 8.3.3.3 Latch-Up Immunity
      4. 8.3.4 1.8V Logic Compatible Inputs
      5. 8.3.5 Integrated Pull-Down Resistor on Logic Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TMUX9612 RUM Package, 16-Pin WQFN (Top View)Figure 5-1 RUM Package, 16-Pin WQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME WQFN
D1 16 I/O Drain pin 1. Can be an input or output.
D2 13 I/O Drain pin 2. Can be an input or output.
D3 8 I/O Drain pin 3. Can be an input or output.
D4 5 I/O Drain pin 4. Can be an input or output.
GND 3 P Ground (0 V) reference
S1 15 I/O Source pin 1. Can be an input or output.
S2 14 I/O Source pin 2. Can be an input or output.
S3 7 I/O Source pin 3. Can be an input or output.
S4 6 I/O Source pin 4. Can be an input or output.
SEL1 2 I Logic control input 1.
SEL2 12 I Logic control input 2.
SEL3 11 I Logic control input 3.
SEL4 4 I Logic control input 4.
VOUT 10 P Internally generated voltage output rail. For reliable operation, connect a decoupling capacitor ranging from 0.01µF to 0.1µF between VOUT and GND on pin 10 or on the thermal pad. Having the decoupling capacitor as close to the thermal pad as possible yeilds the best performance.
VDD 9 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 1µF to 10µF between VDD and GND.
VSS 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 1µF to 10µF between VSS and GND.
Thermal Pad (VOUT) P The thermal pad is internally connected to VOUT (same node as pin 10). VOUT is an internally generated voltage output rail. For reliable operation, connect a decoupling capacitor ranging from 0.01µF to 0.1µF between VOUT and GND on pin 10 or on the thermal pad. Having the decoupling capacitor as close to the thermal pad as possible yeilds the best performance.
(1) I = input, O = output, I/O = input and output, P = power