SLOS841B September   2013  – January 2015 TPA3131D2 , TPA3132D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Gain Setting and Master and Slave
      2. 7.3.2  Input Impedance
      3. 7.3.3  Start-up/Shutdown Operation
      4. 7.3.4  PLIMIT Operation
      5. 7.3.5  GVDD Supply
      6. 7.3.6  BSPx and BSNx Capacitors
      7. 7.3.7  Differential Inputs
      8. 7.3.8  Device Protection System
      9. 7.3.9  DC Detect Protection
      10. 7.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 7.3.11 Thermal Protection
      12. 7.3.12 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      13. 7.3.13 Ferrite Bead Filter Considerations
      14. 7.3.14 When to Use an Output Filter for EMI Suppression
      15. 7.3.15 AM Avoidance EMI Reduction
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mono Mode (PBTL)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the PWM Frequency
        2. 8.2.2.2 Select the Amplifier Gain and Master/Slave Mode
        3. 8.2.2.3 Select Input Capacitance
        4. 8.2.2.4 Select Decoupling Capacitors
        5. 8.2.2.5 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Design
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RHB Packaged
32-Pin VQFN With Exposed Thermal Pad
Top View
QFN-32_Pinout.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.
2 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1uF X7R ceramic decoupling capacitor.
3 GAIN/SLV I Sets Gain and selects between Master and Slave mode depending on pin voltage divider.
4 GND G Ground
5 INNL I Negative audio input for left channel. Biased at 3V.
6 INPL I Positive audio input for left channel. Biased at 3V.
7 MUTE I Mute signal for fast disable/enable of outputs: HIGH = outputs OFF (high-Z), LOW = outputs ON. TTL logic levels with compliance to AVCC.
8 AM2 I AM Avoidance Frequency Selection
9 AM1 I AM Avoidance Frequency Selection
10 AM0 I AM Avoidance Frequency Selection
11 SYNC DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV pin. Input signal not to exceed GVDD (7V)
12 AVCC P Analog Supply
13 PVCC P Power supply
14 PVCC P Power supply
15 BSPL BST Boot strap for positive left channel output, connect to 220nF X7R ceramic cap to OUTPL
16 OUTPL PO Positive left channel output
17 GND G Ground
18 OUTNL PO Negative left channel output
19 BSNL BST Boot strap for negative left channel output, connect to 220nF X7R ceramic cap to OUTNL
20 GND G Ground
21 GND G Ground
22 BSNR BST Boot strap for negative right channel output, connect to 220nF X7R ceramic cap to OUTNR
23 OUTNR PO Negative right channel output
24 GND G Ground
25 OUTPR PO Positive right channel output
26 BSPR BST Boot strap for positive right channel output, connect to 220nF X7R ceramic cap to OUTPR
27 PVCC PI Power supply
28 PVCC PI Power supply
29 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
30 FAULTZ DO General fault reporting including Over-current_PVCC, OVP_DVDD
FAULT1Z = High, normal operation
FAULT1Z = Low, fault condition
31 INPR I Positive audio input for right channel. Biased at 3V.
32 INNR I Negative audio input for right channel. Biased at 3V.
33 Thermal pad G Connect to GND for best system performance. If not connected to GND, leave floating.
(1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.