SLOS597B December   2008  – July 2017 TPA6132A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Condtions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Headphone Amplifiers
      2. 7.3.2 Eliminating Turn-on Pop and Power Supply Sequencing
      3. 7.3.3 RF and Power Supply Noise Immunity
      4. 7.3.4 Constant Maximum Output Power and Acoustic Shock Prevention
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gain Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Configuration with Differential Input Signals
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Coupling Capacitors
          2. 8.2.1.2.2 Charge Pump Flying Capacitor and HPVSS Capacitor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Configuration with Single-Ended Input Signals
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply and HPVDD Decoupling Capacitors
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 GND Connections
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, TA = 25°C (unless otherwise noted)
MIN MAX UNIT
Supply voltage VDD –0.3 6 V
Headphone amplifier supply voltage HPVDD (do not connect to external supply) –0.3 1.9 V
Input voltage, VI INR+, INR-, INL+, INL- HPVSS –0.3 HPVDD + 0.3 V
EN, G0, G1 –0.3 VDD + 0.3 V
Output continuous total power dissipation See Thermal Information
Operating free-air temperature range, TA –40 85 °C
Operating junction temperature range, TJ –40 150 °C
Storage temperature range, Tstg –65 85 °C

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) OUTL, OUTR ±8000 V
All Other Pins ±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Condtions

MIN MAX UNIT
Supply voltage, VDD 2.3 5.5 V
VIH High-level input voltage; EN, G0, G1 1.3 V
VIL Low-level input voltage; EN, G0, G1 0.6 V
VI Input voltage; INR+, INR-, INL+, INL- 0 HPVDD + 0.3 V
Voltage applied to Output; OUTR, OUTL (when EN = 0 V) –0.3 3.6 V
TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) RTE UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 51.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.9
RθJB Junction-to-board thermal resistance 24.3
ψJT Junction-to-top characterization parameter 0.9
ψJB Junction-to-board characterization parameter 24.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 9.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output offset voltage –0.5 0.5 mV
Power supply rejection ratio VDD = 2.3 V to 5.5 V 100 dB
High-level output current (EN, G0, G1) 1 µA
Low-level output current (EN, G0, G1) 1 µA
Supply Current VDD = 2.3 V, No load, EN = VDD 2.1 3.1 mA
VDD = 3.6 V, No load, EN = VDD 2.1 3.1
VDD = 5.5 V, No load, EN = VDD 2.2 3.2
EN = 0 V, VDD = 2.3 V to 5.5 V 0.7 1.2 µA

6.6 Operating Characteristics

VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power(1) (Outputs in phase) THD = 1%, f = 1 kHz 25 mW
THD = 1%, f = 1 kHz, RL = 32 Ω 22
VO Output voltage (1) (Outputs in phase) THD = 1%, VDD = 3.6 V, f = 1 kHz, RL = 100 Ω 1.1 VRMS
AV Closed-loop voltage gain (OUT / IN–) G0 = 0 V, G1 = 0 V, (–6 dB) –0.45 –0.5 –0.55 V/V
G0 ≥ 1.3 V, G1 = 0 V, (0 dB) –0.95 –1.0 –1.05
G0 = 0 V, G1 ≥ 1.3 V, (3 dB) –1.36 –1.41 –1.46
G0 ≥ 1.3 V, G1 ≥ 1.3 V, (6 dB) –1.95 –2.0 –2.05
ΔAv Gain matching Between Left and Right channels 1%
RIN Input impedance (per input pin) G0 = 0 V, G1 = 0 V, (–6 dB) 26.4 kΩ
G0 ≥ 1.3 V, G1 = 0 V, (0 dB) 19.8
G0 = 0 V, G1 ≥ 1.3 V, (3 dB) 16.5
G0 ≥ 1.3 V, G1 ≥ 1.3 V, (6 dB) 13.2
Input impedance in shutdown
(per input pin)		 EN = 0 V 10
VCM Input common-mode voltage range –0.5 1.5 V
Output impedance in shutdown 20 Ω
Input-to-output attenuation in shutdown EN = 0 V 80 dB
kSVR AC-power supply rejection ratio 200 mVpp ripple, f = 217 Hz -100 dB
200 mVpp ripple, f = 10 kHz -90
THD+N Total harmonic distortion plus noise(2) PO = 20 mW, f = 1 kHz 0.02%
PO = 25 mW into 32 Ω, VDD = 5.5 V, f = 1 kHz 0.01%
SNR Signal-to-noise ratio PO = 20 mW; G0 ≥ 1.3 V, G1 = 0 V, (AV = 0 dB) 100 dB
En Noise output voltage A-weighted 5.5 μVRMS
fosc Charge pump switching frequency 1200 1275 1350 kHz
tON Start-up time from shutdown 5 ms
Crosstallk PO = 20 mW, f = 1 kHz –80 dB
Thermal shutdown Threshold 150 °C
Hysteresis 20 °C
(1) Per output channel
(2) A-weighted

6.7 Typical Characteristics

TA = 25°C, VDD = 3.6 V, Gain = 0 dB, EN = 3.6 V, CHPVDD = CHPVSS = 2.2 μF, CINPUT = CFLYING = 1 μF, Outputs in Phase

TPA6132A2 thdn_po_los597.gif Figure 1. Total Harmonic Distortion + Noise vs
Output Power
TPA6132A2 thdn_f_los597.gif Figure 3. Total Harmonic Distortion + Noise vs Frequency
TPA6132A2 thdn3_f_los597.gif Figure 5. Total Harmonic Distortion + Noise vs Frequency
TPA6132A2 thdn5_f_los597.gif
Figure 7. Total Harmonic Distortion + Noise vs Frequency
TPA6132A2 po_vdd_los597.gif
Figure 9. Output Power vs Supply Voltage
TPA6132A2 po_rl_los597.gif
Figure 11. Output Power vs Load Resistance
TPA6132A2 vo_vdd_los597.gif
Figure 13. Output Voltage vs Supply Voltage
TPA6132A2 ksvr2_f_los597.gif
Figure 15. Supply Voltage Rejection Ratio vs Frequency
TPA6132A2 idd_po_los597.gif
Figure 17. Supply Current vs Total Output Power
TPA6132A2 crosstalk_los597.gif
Figure 19. Crosstalk vs Frequency
TPA6132A2 v_t_los597.gif
Figure 21. Startup Waveforms vs Time
TPA6132A2 thdn2_po_los597.gif Figure 2. Total Harmonic Distortion + Noise vs
Output Power
TPA6132A2 thdn2_f_los597.gif Figure 4. Total Harmonic Distortion + Noise vs Frequency
TPA6132A2 thdn4_f_los597.gif Figure 6. Total Harmonic Distortion + Noise vs Frequency
TPA6132A2 thdn6_f_los597.gif
Figure 8. Total Harmonic Distortion + Noise vs Frequency
TPA6132A2 po2_vdd_los597.gif
Figure 10. Output Power vs Supply Voltage
TPA6132A2 po2_rl_los597.gif
Figure 12. Output Power vs Load Resistance
TPA6132A2 ksvr_f_los597.gif
Figure 14. Supply Voltage Rejection Ratio vs Frequency
TPA6132A2 que_vdd_los597.gif
Figure 16. Quiescent Supply Current vs Supply Voltage
TPA6132A2 idd2_po_los597.gif
Figure 18. Supply Current vs Total Output Power
TPA6132A2 vo_f_los597.gif
Figure 20. Output Spectrum vs Frequency
TPA6132A2 v2_t_los597.gif
Figure 22. Shutdown Waveforms vs Time