SLVSBQ8D December   2012  – October 2023 TPD4E1B06

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ultra Low Leakage Current 0.5 nA (Maximum)
      2. 7.3.2 Transient Protection for 4 I/O Lines
      3. 7.3.3 I/O Capacitance 0.7 pF (Typical)
      4. 7.3.4 Bi-Directional (ESD) Protection Diode Array
      5. 7.3.5 Low ESD Clamping Voltage
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on IO1, IO2, IO3, and IO4 Pins
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Layout Examples

Figure 8-3 shows a layout example for theTPD4E1B06DCK. Pins 1 and 2 and 4 and 5 are routed differentially. Pin 3 is routed to the ground plane. Pin 6 does not have an internal connection in the device and does not need to be routed anywhere on the board. It is also acceptable to connect pin 6 to the ground plane.

GUID-808BBB37-0045-4035-8EAD-DA1298BDE63D-low.gifFigure 8-3 DCK Layout Example Showing Two Data Pairs, D0 and D1

Figure 8-4 shows a layout example for theTPD4E1B06DRL. Pins 1 and 6 and 3 and 4 are routed differentially. Pin 2 is routed to the ground plane. Pin 5 does not have an internal connection in the device and does not need to be routed anywhere on the board. It is also acceptable to connect pin 5 to the ground plane.

GUID-59769038-73B2-4CF0-ABDC-52CAA03707C9-low.gifFigure 8-4 DRL Layout Example Showing Two Data Pairs, D0 and D1