SLLS800B June   2010  – May 2021 TPD4F202 , TPD6F202

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings — JEDEC
    3. 6.3 ESD Ratings — IEC
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Exceeds IEC61000-4-2 (Level 4) ESD Protection Requirements
      2. 7.3.2 Pi-Style C-R-C Filter Configuration
      3. 7.3.3 Low 10-nA Leakage Current
      4. 7.3.4 Space-Saving DSBGA Package
        1. 7.3.4.1 Flow-Through Pin Mapping
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1.      26
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on All Protected Lines
        2. 8.2.2.2 Data Rate
        3. 8.2.2.3 ESD Protection Level
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Low 10-nA Leakage Current

The I/O pins feature an ultra-low leakage current of 10 nA (typical) with a bias of 3.3 V.