SLIS166 July   2015 TPIC2060A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Serial I/F Write Timing Requirements
    7. 7.7 Serial I/F Read Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Functions
        1. 8.3.1.1 OVP
        2. 8.3.1.2 SCP
        3. 8.3.1.3 Temperature Shutdown (TSD)
        4. 8.3.1.4 ACTTIMER
    4. 8.4 Device Functional Modes
      1. 8.4.1 Differential Tilt Mode
      2. 8.4.2 Power-On Reset (POR)
        1. 8.4.2.1 RDY (Power Ready)
        2. 8.4.2.2 Voltage Monitoring
    5. 8.5 Programming
      1. 8.5.1 Serial Port Functional Description
      2. 8.5.2 Write Operation
      3. 8.5.3 Read Operation
      4. 8.5.4 Write and Read Operation
    6. 8.6 Register Maps
      1. 8.6.1 Register State Transition
      2. 8.6.2 DAC Register (12-Bit Write Only)
      3. 8.6.3 Control Register (8-Bit Read/Write)
      4. 8.6.4 Detailed Register Description
        1. 8.6.4.1  REG01 12-Bit DAC for Tilt (offset = 01h)
        2. 8.6.4.2  REG02 12-Bit DAC for Focus (offset = 02h)
        3. 8.6.4.3  REG03 12-Bit DAC for Tracking (offset = 03h)
        4. 8.6.4.4  REG04 12-Bit DAC for Sled1 (offset = 04h)
        5. 8.6.4.5  REG05 12-Bit DAC for Sled2 (offset = 05h)
        6. 8.6.4.6  REG06 12-Bit DAC for Stepping1 (offset = 06h)
        7. 8.6.4.7  REG07 12-Bit DAC for Stepping2 (offset = 07h)
        8. 8.6.4.8  REG08 12-Bit DAC for Spindle (offset = 08h)
        9. 8.6.4.9  REG09 12-Bit DAC for Load (offset = 09h)
        10. 8.6.4.10 REG70 8-Bit Control Register for DriverEna (offset = 70h)
        11. 8.6.4.11 REG71 8-Bit Control Register for FuncEna (offset = 71h)
        12. 8.6.4.12 REG72 8-Bit Control Register for ACTCfg (offset = 72h)
        13. 8.6.4.13 REG73 8-Bit Control Register for Parm0 (offset = 73h)
        14. 8.6.4.14 REG74 8-Bit Control Register for SIFCfg (offset = 74h)
        15. 8.6.4.15 REG75 8-Bit Control Register for Parm1 (offset = 75h)
        16. 8.6.4.16 REG76 8-Bit Control Register for WriteEna (offset = 76h)
        17. 8.6.4.17 REG77 8-Bit Control Register for ClrReg (offset = 77h)
        18. 8.6.4.18 REG78 8-Bit Control Register for ActTemp (offset = 78h)
        19. 8.6.4.19 REG79 8-Bit Control Register for UVLOMon (offset = 79h)
        20. 8.6.4.20 REG7A 8-Bit Control Register for TSDMon (offset = 7Ah)
        21. 8.6.4.21 REG7B 8-Bit Control Register for SCPMon (offset = 7Bh)
        22. 8.6.4.22 REG7C 8-Bit Control Register for TempMon (offset = 7Ch)
        23. 8.6.4.23 REG7D 8-Bit Control Register for Status Monitor (offset = 7Dh)
        24. 8.6.4.24 REG7E 8-Bit Control Register for Version (offset = 7Eh)
        25. 8.6.4.25 REG7F 8-Bit Control Register for Status (offset = 7Fh)
        26. 8.6.4.26 REG60 8-Bit Control Register for SPMCfg (offset = 60h)
        27. 8.6.4.27 REG61 8-Bit Control Register for SPMCfg (offset = 61h)
        28. 8.6.4.28 REG62 8-Bit Control Register for SPMCfg (offset = 62h)
        29. 8.6.4.29 REG64 8-Bit Control Register for Protect (offset = 64h)
        30. 8.6.4.30 REG65 8-Bit Control Register for SPMCfg (offset = 65h)
        31. 8.6.4.31 REG68 8-Bit Control Register for Protect (offset = 68h)
        32. 8.6.4.32 REG6B 8-Bit Control Register for DisProt (offset = 6Bh)
        33. 8.6.4.33 REG6C 8-Bit Control Register for ENDCfg (offset = 6Ch)
        34. 8.6.4.34 REG6E 8-Bit Control Register for UtilCfg (offset = 6Eh)
        35. 8.6.4.35 REG6F 8-Bit Control Register for GPOUTSet (offset = 6Fh)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  DAC Type
      2. 9.1.2  Example of 12-Bit DAC Sampling Rate for FCS/TRK/TLT
      3. 9.1.3  Digital Input Coding
      4. 9.1.4  Example Timing of Target Control System
      5. 9.1.5  Spindle Motor Driver Operating Sequence
      6. 9.1.6  Auto Short Brake Function
      7. 9.1.7  Spindle PWM Control
      8. 9.1.8  Spindle Driver Current Limit Circuit
      9. 9.1.9  Sled Driver Part
      10. 9.1.10 Stepping Driver Part
      11. 9.1.11 Focus/Track/Tilt Driver Part
        1. 9.1.11.1 Input VS Output Duty
      12. 9.1.12 Load Driver Part
      13. 9.1.13 End Detect Function
      14. 9.1.14 Load Tray Lock Detect Function
      15. 9.1.15 Load Tray Push Detect Function
      16. 9.1.16 Monitor Signal on GPOUT
      17. 9.1.17 9-V LDO
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPIC2060A is a low-noise motor driver IC suitable for 12-V ODD. The 9-channel driver IC controlled by a serial interface is optimized for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, focus / tracking / tilt actuators, and stepping motor for collimator lens. This IC has an integrated current sense resistance that measures SPM current, which reduces drive system costs. The spindle motor driver part builds in sensorless logic, which attains low-noise operation at the start and run times. The user does not need to self-start the device using the starting circuit or perform position detection by BEMF of a motor or sensors such as a Hall device. As the output stage of all channels works in efficient PWM driving, the user can attain low-power operation by PWM control. Dead-zone-less control is possible for a focus / tracking / tilt actuator driver. In addition, the spindle part output current limiting circuit, the thermal shutdown circuit, the sled-end detection circuit, collimator-lens-end detection circuit, actuator protection, and pre-driver for a 9-V LDO are built in. The newly added, built-in thermometer measures IC temperature.

8.2 Functional Block Diagram

TPIC2060A slis166_fbd.gif

8.3 Feature Description

8.3.1 Protection Functions

The TPIC2060A has four protection features to protect target equipment: overvoltage protection (OVP), short-circuit protection (SCP), thermal protection (TSD), and actuator temperature protection (ACTTIMER).

8.3.1.1 OVP

The OVP function protects the unit from the supplying high voltage. When the supply voltage exceeds 6.2 V (for P5V), all driver output goes Hi-Z. SPM, sled, and load channels put Hi-Z when P12V is over 14.9 V. Regardless of the input voltage of P5V12L, the load channel become Hi-Z at the time of OVP_P5V or OVP_P12V. When the supply voltage falls below a typical 6.0 V, all outputs start to operate again. (14.5 V for 12-V driver channel) The OVP and POR (RDY) function is not interlocking.

OVP is intended to protect the device in evaluation stage as temporary and back-up solution.

8.3.1.2 SCP

SCP protects the device from breakdown by large current. Each behavior is indicated on Table 1.

Table 1. Protection Threshold Table

BLOCK FUNCTION DETECTION CURRENT DETECT TIME HI-Z HOLD TIME
STEP driver SCP

Monitor driver output voltage

Hi side FET output V = GND

Lo side FET output V = Supply voltage

 0.8 to 1.6 µs 1.6 ms
SPM driver
Sled driver
Load driver
Actuator driver

When the large current is detected on each block, the device puts the output FET to Hi-Z.

When SCP occurs, it returns automatically after expiring set Hi-Z hold time. The OCPSCPERR (REG7F) and SCP flag (REG7B) are set at detection.

The SCP function always monitors the output voltage of the high-side and low-side FET of the output driver. When the setting voltage is not outputted, the device recognizes it as SCP and changes output Hi-Z. The device returns to the original state automatically after 1.6 ms.

TPIC2060A slis166_ex_scp_driver_shrt_gnd.gif Figure 6. Example of SCP (Driver Short to GND)

8.3.1.3 Temperature Shutdown (TSD)

TSD is a protection function which intercepts an output and suspends an operation when the IC temperature exceeds a maximum permissible on a safety. TSD makes an output Hi-Z when the temperature rises up and a threshold value is exceeded. There are two levels for threshold: Alert and Trip. An alarm is given by status register TSD_FAULT_ on Alert level with 135°C. If it the temperature continues to rise, the register TSD_ is set at 150°C, and the driver output changes HI-Z. If the temperature falls and reaches 135°C, it will output again. The TPIC2060A has 11 temperature sensors in each circuit block. Particular sensors are assigned to the appropriate status flags in Table 2.

Table 2. Thermal Sensor Assignment

CIRCUIT ALERT (°C) TRIP (°C) RELEASE (°C) ALERT FLAG TRIP FLAG
U 135 150 135 TSD_FAULT_SPM TSD_SPM
V 135 150 135 TSD_FAULT_SPM TSD_SPM
W 135 150 135 TSD_FAULT_SPM TSD_SPM
TLT 135 150 135 TSD_FAULT_ACT TSD_ACT
FCS 135 150 135 TSD_FAULT_ACT TSD_ACT
TRK 135 150 135 TSD_FAULT_ACT TSD_ACT
SLED1 135 150 135 TSD_FAULT_ACT TSD_ACT
SLED2 135 150 135 TSD_FAULT_ACT TSD_ACT
STP 135 150 135 TSD_FAULT_ACT TSD_ACT
LOAD 135 150 135 TSD_FAULT_ACT TSD_ACT
P12DCHG 135 150 135 TSD_FAULT_P12DCHG TSD_P12DCHG

8.3.1.4 ACTTIMER

The TPIC2060A has an actuator protection function named ACTTIMER. This function sets the actuator channel output to Hi-Z when the actuator coil current exceeds a specific value. Some other devices use a simple actuator protection function that detects if max current is exceeded with time; however, this other type of actuator protection function lacks accuracy. This new protection calculates heat accumulation and judges accordingly. When this function operates, the load driver channel output will be Hi-Z, the spindle channel is forced to “Auto short brake” and the disc motor stops.

Observe if the protection has occurred by checking the Fault register ACTTIMER_FAULT and ACT_TIMER_PROT. ACTTIMER_FAULT has a character for advance notice, set before detecting ACT_TIMER_PROT. After an ACT_TIMER_PROT is set, even if the temperature falls, it will not release the protection automatically. It is necessary to clear the flag by setting RST_ERR_FLAG or setting 0 to ACTTEMPTH. The ACTTIMER function is disabled by setting H to ACTPROT_OFF or setting 0 to ACTTEMPTH.

To acquire the optimal value for ACTTEMPTH, set the device into the condition of the detection level, and read the value of ACTTEMP. The present value can be read from ACTTEMP. The ACTTEMP data is updated in the register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.

TPIC2060A slis166_actuator_temp_prot.gif Figure 7. Actuator Temperature Protections

8.4 Device Functional Modes

8.4.1 Differential Tilt Mode

The TPIC2060A supports differential tilt mode, which outputs the value calculated from focus and tilt. Focus and tilt can be set in differential mode by DIFF_TLT (REG74) = 1. Because focus and tilt are updated at the same time, the update interval of tilt can be thinned out. Output data changes at after writing VFCS data. Therefore, it is necessary to write VFCS data when setting VTLT. In differential mode, the output value is calculated as follows.

Equation 1. FCS_OUT = (VFCS + VTLT) × 6
Equation 2. TLT_OUT = (VFCS – VTLT) × 6

8.4.2 Power-On Reset (POR)

8.4.2.1 RDY (Power Ready)

The TPIC2060A prepares the RDY pin to show a power status to the host controller. A device sets RDY output to high (= POR), if the supply voltage and internal regulator voltage reach a rated value. All registers are initialized at the time of POR operation. Figure 8 shows the behavior of RDY.

TPIC2060A slis166_10_rdy_pin_beh.gif
A. *1 = The period of XRSTIN cannot be communicated with the device.
Figure 8. 10 RDY Pin Behavior

8.4.2.2 Voltage Monitoring

Power faults are reported in the UVLOMon register. Each UVLOMon bit is initialized to 0 upon a cold power-up. After a fault is detected, the appropriate fault bit is latched high. Writing to the RST_ERR_FLG (REG77) clears all UVLOMon bits. Table 3 summarizes the power device faults and actions.

Table 3. Power Fault Monitor

FAULT TYPE LATCHED REGISTER POR CRITERIA DRIVER OUTPUT AT DETECTION
SPM SLED LOAD STEP ACT
P5V under voltage UVLO_P5V Yes <3.7 V Hi-Z
Internal 3.3 V under voltage UVLO_INT3P3 Yes <2.7 V Hi-Z
P12V under voltage UVLO_P12V Yes(1) <8.4 V Hi-Z
SIOV under voltage UVLO_SIOV Yes <2.0 V Hi-Z
P5V over voltage OVP_P5V >6.2 V Hi-Z
P12V over voltage OVP_P12V >14.9 V Hi-Z — —
(1) P12VMUTE_NORST = 0: force POR, P12VMUTE_NORST = 1: no POR

8.5 Programming

8.5.1 Serial Port Functional Description

The serial communication of the TPIC2060A is based on a SPI communications protocol. TPIC2060A is put on the slave side. All 16-bit transmission data is effective in SSZ = L period.

The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge of SCLK. All data is transmitted in a 16-bit format of a command and data. A format has two types of data, 8 bits and 12 bits in length. To access specific registers, an address and R/W flag are specified as a command part. In addition, 12-bit data types do not have a R/W flag in the packet, as the DAC register　(= 12-bit data form) is Write only. A transfer packet, command and data, is transmitted sequentially from MSB to LSB. A packet is distinguished in MSB 2 bits of command. In the case of 11, it handles a packet for control register access, and the other processed as a packet for a DAC data setting.

These are the four kinds of serial-data communication packets:

  • Write 12 bits DAC data (MSB two bit ≠ 11)
  • Write 8 bits control register (MSB two bit = 11)
  • Read 8 bits control register (MSB two bit = 11)
  • Write 12 bits Focus DAC data＋Read 8 bits status register at the same time (MSB two bit ≠ 11)

8.5.2 Write Operation

For write operations, DSP transmits 16-bit (command + address + data) data in an order from MSB. Only the 16-bit data, 16 SCLK sent from the master during SSZ = L, is effective. If >17 or <15 SCLK pulses are received during the time that SSZ is low, the whole packet is ignored. For all valid write operations, the data of the shift register is latched into its designated internal register at the rising edge of the 16th SCLK. All internal register bits, except as indicated otherwise, are reset to their default states upon power-on reset.

TPIC2060A slis166_write_12_bits_dac_data.gif Figure 9. Write 12 Bits DAC Data
TPIC2060A slis166_write_8_bits_ctrl_reg.gif Figure 10. Write 8 Bits Control Register

8.5.3 Read Operation

DSP sends an 8-bit header through SIMO to perform the Read operation. The TPIC2060A starts to drive the SOMI line upon the eighth falling edge of SCLK and shifts out eight data bits. The master DSP inputs 8 bits of data from SOMI after the ninth rising edge of SCLK. 　

TPIC2060A slis166_read_8_bits_ctrl_reg.gif Figure 11. Read 8 Bits Control Register

8.5.4 Write and Read Operation

Optionally, the master DSP can read the Status register during writing a 12 bits DAC (Focus DAC) packet. It is enabled by setting bit RDSTAT_ON_VFCS (REG74) = H.

TPIC2060A slis166__write_12_bits_read_8_bits.gif Figure 12. Write 12 Bits Focus DAC Data + Read 8 Bits Status Data

8.6 Register Maps

All registers are in WRITE-protect mode after XRSTIN release. WRITE_ENA bit (REG76) = 1 is required before writing data in register.

8.6.1 Register State Transition

TPIC2060A slis166_reg_behavior.gif Figure 13. Register Behavior

8.6.2 DAC Register (12-Bit Write Only)

Two different forms are prepared in the 12-bit DAC register. The forms are selected by setting VDAC_MAPSW (REG74h).

Table 4. List 2 DAC Register (VDAC_MAPSW = 0)

REG NAME 11 10 9 8 7 6 5 4 3 2 1 0
00h N/A N/A
01h VTLT VTLT
[11]		 VTLT
[10]		 VTLT[9] VTLT[8] VTLT[7] VTLT[6] VTLT[5] VTLT[4] VTLT[3] VTLT[2] VTLT[1] VTLT[0]
02h VFCS VFCS
[11]		 VFCS
[10]		 VFCS[9] VFCS[8] VFCS[7] VFCS[6] VFCS[5] VFCS[4] VFCS[3] VFCS[2] VFCS[1] VFCS[0]
03h VTRK VTRK
[11]		 VTRK
[10]		 VTRK[9] VTRK[8] VTRK[7] VTRK[6] VTRK[5] VTRK[4] VTRK[3] VTRK[2] VTRK[1] VTRK[0]
04h VSLD1 VSLD1
[11]		 VSLD1
[10]		 VSLD1
[9]		 VSLD1
[8]		 VSLD1
[7]		 VSLD1
[6]		 VSLD1
[5]		 VSLD1
[4]		 VSLD1[3] VSLD1[2] VSLD1[1](1) VSLD1[0](1)
05h VSLD2 VSLD2
[11]		 VSLD2
[10]		 VSLD2
[9]		 VSLD2
[8]		 VSLD2
[7]		 VSLD2
[6]		 VSLD2
[5]		 VSLD2
[4]		 VSLD2[3] VSLD2[2] VSLD2[1](1) VSLD2[0](1)
06h VSTP1 VSTP1
[11]		 VSTP1
[10]		 VSTP1
[9]		 VSTP1
[8]		 VSTP1
[7]		 VSTP1
[6]		 VSTP1
[5]		 VSTP1
[4]		 VSTP1[3](1) VSTP1[2](1) VSTP1[1](1) VSTP1[0](1)
07h VSTP2 VSTP2
[11]		 VSTP2
[10]		 VSTP2
[9]		 VSTP2
[8]		 VSTP2
[7]		 VSTP2
[6]		 VSTP2
[5]		 VSTP2
[4]		 VSTP2[3](1) VSTP2[2](1) VSTP2[1](1) VSTP2[0](1)
08h VSPM VSPM
[11]		 VSPM
[10]		 VSPM[9] VSPM[8] VSPM[7] VSPM[6] VSPM[5] VSPM[4] VSPM[3] VSPM[2] VSPM[1] VSPM[0]
09h VLOAD VLOAD
[11]		 VLOAD
[10]		 VLOAD[9] VLOAD[8] VLOAD[7] VLOAD[6] VLOAD[5] VLOAD[4] VLOAD[3] VLOAD[2] VLOAD[1] VLOAD[0]
0Ah N/A N/A
0Bh N/A N/A
(1) TPIC2060A process as 0 even if set as 1.

Table 5. List 3 DAC Register (VDAC_MAPSW=1)

REG NAME 11 10 9 8 7 6 5 4 3 2 1 0
00h N/A N/A
01h VTRK VTRK
[11]		 VTRK
[10]		 VTRK[9] VTRK[8] VTRK[7] VTRK[6] VTRK[5] VTRK[4] VTRK[3] VTRK[2] VTRK[1] VTRK[0]
02h VFCS VFCS
[11]		 VFCS
[10]		 VFCS[9] VFCS[8] VFCS[7] VFCS[6] VFCS[5] VFCS[4] VFCS[3] VFCS[2] VFCS[1] VFCS[0]
03h VTLT VTLT
[11]		 VTLT
[10]		 VTLT[9] VTLT[8] VTLT[7] VTLT[6] VTLT[5] VTLT[4] VTLT[3] VTLT[2] VTLT[1] VTLT[0]
04h VSLD1 VSLD1
[11]		 VSLD1
[10]		 VSLD1
[9]		 VSLD1
[8]		 VSLD1
[7]		 VSLD1
[6]		 VSLD1
[5]		 VSLD1
[4]		 VSLD1
[3]		 VSLD1
[2]		 VSLD1
[1](1)		 VSLD1
[0](1)
05h VSLD2 VSLD2
[11]		 VSLD2
[10]		 VSLD2
[9]		 VSLD2
[8]		 VSLD2
[7]		 VSLD2
[6]		 VSLD2
[5]		 VSLD2
[4]		 VSLD2
[3]		 VSLD2
[2]		 VSLD2
[1](1)		 VSLD2
[0](1)
06h VSPM VSPM
[11]		 VSPM
[10]		 VSPM[9] VSPM[8] VSPM[7] VSPM[6] VSPM[5] VSPM[4] VSPM[3] VSPM[2] VSPM[1] VSPM[0]
07h N/A N/A
08h N/A N/A
09h VLOAD N/A VLOAD
[11]		 VLOAD
[10]		 VLOAD
[9]		 VLOAD
[8]		 VLOAD
[7]		 VLOAD
[6]		 VLOAD
[5]		 VLOAD
[4]
0Ah VSTP1 N/A VSTP1
[11]		 VSTP1
[10]		 VSTP1
[9]		 VSTP1
[8]		 VSTP1
[7]		 VSTP1
[6]		 VSTP1
[5]		 VSTP1
[4]
0Bh VSTP2 N/A VSTP2
[11]		 VSTP2
[10]		 VSTP2
[9]		 VSTP2
[8]		 VSTP2
[7]		 VSTP2
[6]		 VSTP2
[5]		 VSTP2
[4]
(1) TPIC2060A process as 0 even if set as 1.

8.6.3 Control Register (8-Bit Read/Write)

Table 6. List 4 Control Register (8-Bit Read/Write)

REG NAME F 7 6 5 4 3 2 1 0
70h DriverEna R/W TLT_ENA FCS_ENA TRK_ENA SPM_ENA SLD_ENA STP_ENA LOAD_ENA XSLEEP
71h FuncEna R/W TI Rsvd SLD
_ENDDET
_ENA		 STP
_ENDDET
_ENA		 TI Rsvd LIN9V
_DISABLE		 SPM_RCOM_SEL TEMPMON
_ENA
72h ACTCfg R/W P12VMUTE
_NORST		 RSTIN_OFF ACTPROT
_OFF		 ACTTEMPTH
73h Parm0 R/W SIF_TIMEOUT_TH SLEDEND
_HZTIME		 SLDENDTH STPEND
_HZTIME		 STPENDTH
74h SIFCfg R/W DIFF_TLT TI Rsvd STATUS
_ON_VFCS		 VSLD2
_POL		 VSTP2
_POL		 ADVANCE
_RD		 SOMI_HIZ VDAC
_MAPSW
75h Parm1 R/W TRAY_LOCKDET TI Reserved SPM_FAST_BRK SPM_SLNT_BRK SPM
_HIZMODE
76h WriteEna R/W WRITE
_ENABLE		 TI Reserved REG6X
_Write		 TI Rsvd
77h ClrReg W RST_INDAC RST_REGS RST_ERR
_FLAG		 TI Reserved
78h ActTemp R TI Reserved ACT_TIMER
_PROT		 ACTTEMP
79h UVLOMon R LIN9V_RDY TI Rsvd UVLO_P5V UVLO
_INT3P3		 UVLO
_P12V		 UVLO_SIOV OVP_P5V OVP_P12V
7Ah TSDMon R TI Rsvd TSD
_FAULT
_SPM		 TSD
_FAULT
_ACT		 TSD
_FAULT
_P12DCHG		 TI Rsvd TSD_SPM TSD_ACT TSD
_P12DCHG
7Bh SCPMon R TI Reserved SCP_SPM SCP_SLED SCP_LOAD SCP_ACT SCP_STP
7Ch TempMon R CHIPTEMP
_STATUS		 CHIPTEMP
7Dh Monitor R SIF_TIMEOUTERR XRSTIN
_DET		 TI Rsvd TRAY_LOCKDETECT TRAY_PUSHDETP TRAY_PUSHDETN STP
_ENDDET		 SLD
_ENDDET
7Eh Version R Version
7Fh Status R ACTTIMER
_FAULT		 MONITOR TI Rsvd PWRERR TSDERR SCPERR TSDFAULT FG
60h SPMCfg R/W TI Rsvd FG_SBRK
_OFF		 TI Reserved IS_NZONE
_OFF		 TI Rsvd
61h SPMCfg R/W TI Reserved PWMmaxDuty_R_SEL TI Rsvd
62h SPMCfg R/W TI Reserved TIME_BASE_SEL TI Reserved
63h Protect R/W TI Reserved
64h Protect R/W TI Reserved FG5M_OFF TI Reserved
65h SPMCfg R/W TI Reserved HZSVR_SEL TI Reserved
66h Protect R/W TI Reserved
67h Protect R/W TI Reserved
68h Protect R/W TI Reserved SPM_TQAJST
6Bh DisProt R/W SCP_SPM
_OFF		 SCP_SLED
_OFF		 SCP_LOAD
_OFF		 SCP_ACT
_OFF		 SCP_STP
_OFF		 SPM
_RCDDIS		 TI Reserved
6Ch ENDCfg R/W PUSHDETTH PUSHDET_TIME TI Reserved
6Dh Protect R/W TI Reserved
6Eh UtilCfg R/W GPOUT_HL GPOUT
_ENA		 TI Reserved
6Fh GPOUTSet R/W ACTTIMER
_FLT_MON		 MONITOR
_MON		 TI Rsvd PWRERR
_MON		 TSDERR
_MON		 OCPSCPERR_MON TSDFAULT
_MON		 SPMRCD
_BRK_MON

VTRK and VLOAD is exclusive, using the same DAC circuit block.

8.6.4 Detailed Register Description

8.6.4.1 REG01 12-Bit DAC for Tilt (offset = 01h)

(VDAC_MAPSW = 0)

Figure 14. REG01 12-Bit DAC for Tilt
11 10 9 8
VTLT
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VTLT
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. REG01 12-Bit DAC for Tilt Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VTLT W 0h

Digital input code for tilt.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Output is changed by “differential tilt mode (REG74[7])”

TLT_OUT = VTLT × (6.0/2048) (DIFF_TLT = 0)

TLT_OUT = (VFCS-VTLT) × (6.0/2048) (DIFF_TLT = 1)

TLT_OUT should be changed after writing VFCS. In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after writing VFCS.

8.6.4.2 REG02 12-Bit DAC for Focus (offset = 02h)

(VDAC_MAPSW = 0)

Figure 15. REG02 12-Bit DAC for Focus
11 10 9 8
VFCS
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VFCS
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. REG02 12-Bit DAC for Focus Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VFCS W 0h

Digital input code for focus.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Output is changed by differential tilt mode (REG74[7])

FCS_OUT = VFCS × (6.0/2048) (DIFF_TLT = 0)

FCS_OUT = (VFCS + VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

8.6.4.3 REG03 12-Bit DAC for Tracking (offset = 03h)

(VDAC_MAPSW = 0)

Figure 16. REG03 12-Bit DAC for Tracking
11 10 9 8
VTRK
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VTRK
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. REG03 12-Bit DAC for Tracking Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VTRK W 0h

Digital input code for tracking.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

TRK_OUT = VTRK × (6.0 / 2048)

8.6.4.4 REG04 12-Bit DAC for Sled1 (offset = 04h)

(VDAC_MAPSW = 0)

Figure 17. REG04 12-Bit DAC for Sled1
11 10 9 8
VSLD1
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSLD1
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. REG04 12-Bit DAC for Sled1 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VSLD1 W 0h

Digital input code for sled1.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD1[1:0], will be handled with 0.

SLD1_OUT = VSLD1 × (880 mA / 2048)

8.6.4.5 REG05 12-Bit DAC for Sled2 (offset = 05h)

(VDAC_MAPSW = 0)

Figure 18. REG05 12-Bit DAC for Sled2
11 10 9 8
VSLD2
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSLD2
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. REG05 12-Bit DAC for Sled2 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VSLD2 W 0h

Digital input code for sled2.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD2[1:0], will be handled with 0.

SLD2_OUT = VSLD2 × (880 mA / 2048)

8.6.4.6 REG06 12-Bit DAC for Stepping1 (offset = 06h)

(VDAC_MAPSW = 0)

Figure 19. REG06 12-Bit DAC for Stepping1
11 10 9 8
VSTP1
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSTP1
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. REG06 12-Bit DAC for Stepping1 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VSTP1 W 0h

Digital input code for stepping1.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Although VSTP1 is 12-bit width, MSB 8 bits is effective.

Four bits on LSB, VSTP1[3:0], will be handled with 0.

VSTP1_OUT = VSTP1 × (P5V/2048)

8.6.4.7 REG07 12-Bit DAC for Stepping2 (offset = 07h)

(VDAC_MAPSW = 0)

Figure 20. REG07 12-Bit DAC for Stepping2
11 10 9 8
VSTP2
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSTP2
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. REG07 12-Bit DAC for Stepping2 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VSTP2 W 0h

Digital input code for stepping2.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Although VSTP2 is 12-bit width, MSB 8 bits is effective.

Four bits on LSB, VSTP2[3:0], will be handled with 0.

VSTP2_OUT = VSTP2 × (P5V/2048)

8.6.4.8 REG08 12-Bit DAC for Spindle (offset = 08h)

(VDAC_MAPSW = 0)

Figure 21. REG08 12-Bit DAC for Spindle
11 10 9 8
VSPM
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSPM
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. REG08 12-Bit DAC for Spindle Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VSPM W 0h

Digital input code for spindle.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

SPM_OUT = VSPM × (14.0/2048)

8.6.4.9 REG09 12-Bit DAC for Load (offset = 09h)

(VDAC_MAPSW = 0)

Figure 22. REG09 12-Bit DAC for Load
11 10 9 8
VLOAD
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VLOAD
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. REG09 12-Bit DAC for Load Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
11-0 VLOAD W 0h

Digital input code for load.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

LOAD_OUT = VLOAD × (6.0 / 2048) at P5V12L = 5.0 V

LOAD_OUT = VLOAD × (14.0 / 2048) at P5V12L = 12.0 V

8.6.4.10 REG70 8-Bit Control Register for DriverEna (offset = 70h)

Figure 23. REG70 8-Bit Control Register for DriverEna
7 6 5 4 3 2 1 0
TLT_ENA FCS_ENA TRK_ENA SPM_ENA SLD_ENA STP_ENA LOAD_ENA XSLEEP
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. REG70 8-Bit Control Register for DriverEna Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 TLT_ENA RW 0h 1h = Tilt enable (with XSLEEP = 1)
6 FCS_ENA RW 0h 1h = Focus enable (with XSLEEP = 1)
5 TRK_ENA RW 0h 1h = Track enable (with XSLEEP = 1)
4 SPM_ENA RW 0h 1h = Spindle enable (with XSLEEP = 1)
3 SLD_ENA RW 0h 1h = Sled enable (with XSLEEP = 1)
2 STP_ENA RW 0h 1h = Step enable (with XSLEEP = 1)
1 LOAD_ENA RW 0h

1h = LOAD enable (with XSLEEP = 1)

Track (bit5:TRK_ENA) will be disabled at LOAD_ENA = 1 because of sharing the DAC PWM module. Load priority is higher than TRK_ENA.

0 XSLEEP RW 0h

1h = Operation mode (need 1 ms)

0h = Standby mode

Charge pump enable bit.

All driver enable bit (Bit[7:1]) change disabled and output change to Hi-Z (regardless of setting xxx_ENA bit is 1) when setting XSLEEP to 0. Therefore, set 1 to XSLEEP before setting each enable bit.

8.6.4.11 REG71 8-Bit Control Register for FuncEna (offset = 71h)

Figure 24. REG71 8-Bit Control Register for FuncEna
7 6 5 4 3 2 1 0
Reserved SLD_ENDDET_ENA STP_ENDDET_ENA Reserved LIN9V
_DISABLE		 SPM_RCOM_SEL TEMPMON
_ENA
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. REG71 8-Bit Control Register for FuncEna Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved RW 0h
6 SLD_ENDDET_ENA RW 0h 1h = Enable SLED channel end position detection (with XSLEEP = 1, SLD_ENA)
5 STP_ENDDET_ENA RW 0h 1h = Enable STEP channel end position detection (with XSLEEP = 1, STP_ENA)
4 Reserved RW 0h
3 LIN9V_DISABLE RW 0h 1h = Disable LDO predriver
2-1 SPM_RCOM_SEL RW 0h

Select resistor value of spindle current sense resistor. Current limit is set as following current (with SPM_TQAJST = 00)

00: 1133 mA

01: 772 mA

10: 1416 mA

11: 1700 mA

0 TEMPMON_ENA RW 0h 1h = Enable chip temperature monitoring (with XSLEEP = 1)

8.6.4.12 REG72 8-Bit Control Register for ACTCfg (offset = 72h)

Figure 25. REG72 8-Bit Control Register for ACTCfg
7 6 5 4 3 2 1 0
P12VMUTE
_NORST		 RSTIN_OFF ACTPROT
_OFF		 ACTTEMPTH
rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. REG72 8-Bit Control Register for ACTCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 P12VMUTE_NORST RW 0h

0h = System reset at P12V low voltage

1h = Output High-Z only at P12V low-voltage detection
6 RSTIN_OFF RW 0h

0h = XRSTIN input enable

1h = Ignored XRSTIN pin input (do not reset device when XRSTIN = L)
5 ACTPROT_OFF RW 0h

0h = Actuator protection ON

1h = Actuator fault monitor disable (no protection for ACT channel)
4-0 ACTTEMPTH RW 0h

Actuator thermal protection (= ACT Timer) threshold level

ACT Timer Protection enable except ACTTEMPTH[4:0] = 0x00

ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1

By writing value 0x00, ACTTIMER_PROT flag is cleared.

8.6.4.13 REG73 8-Bit Control Register for Parm0 (offset = 73h)

Figure 26. REG73 8-Bit Control Register for Parm0
7 6 5 4 3 2 1 0
SIF_TIMEOUT_TH SLEDEND
_HZTIME		 SLDENDTH STPEND
_HZTIME		 STPENDTH
rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. REG73 8-Bit Control Register for Parm0 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-6 SIF_TIMEOUT_TH RW 0h

Watch dog timer for Serial communication

0h = Disable

1h = 1 ms

2h = 100 µs

3h = 10 µs

Set SIF_TIMEOUTERR (REG7D) if communication is suspended for this time period. Reset register processing is performed if a SIF_TIMEOUTERR occurs.

5 SLEDEND_HZTIME RW 0h

Time window for sled end detection.

0h = 400 µs

1h = 200 µs

Note: The user must recycle SLD_ENDDET_ENA = 0 → 1 after writing this bit.

4-3 SLDENDTH RW 0h

Sled end detection sensibility setting. Detection threshold for motor BEMF

00: 124 mV

01: 168 mV

11: 72 mV　

10: 0 mV (use for test purpose)

2 STPEND_HZTIME RW 0h

Step High-Z detection period in end detection

0h = 400 µs

1h = 200 µs

Note: The user must recycle STP_ENDDET_ENA = 0→1 after writing this bit.

1-0 STPENDTH RW 0h

Step end detection sensibility setting

00: 39 mV

01: 61 mV

11: 19 mV

10: 0 mV (use for test purpose)

8.6.4.14 REG74 8-Bit Control Register for SIFCfg (offset = 74h)

Figure 27. REG74 8-Bit Control Register for SIFCfg
7 6 5 4 3 2 1 0
DIFF_TLT Reserved STATUS_ON
_VFCS		 VSLD2_POL VSTP2_POL ADVANCE_RD SOMI_HIZ VDAC_MAPSW
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. REG74 8-Bit Control Register for SIFCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 DIFF_TLT RW 0h

1h = Differential tilt mode enable (with TLT_ENA = FCS_ENA = 1)

Differential tilt mode (DIFF_TLT = 1), DAC value setting as follows

FCS_OUT = (VFCS + VTLT) × 6 / 2048

TLT_OUT = (VFCS – VTLT) × 6 / 2048

In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after writing VFCS.

6 Reserved RW 0h
5 STATUS_ON_VFCS RW 0h

Set Read status data (REG7F) at VFCS write command (REG02)

1h = enable Write and Read mode

(Write 12 bits Focus DAC data + Read 8 bits status data)

4 VSLD2_POL RW 0h Change direction of SLED rotation
3 VSTP2_POL RW 0h Change direction of STEP rotation
2 ADVANCE_RD RW 0h

0h = Normal read timing

1h = Read timing is advanced half clock cycle

1 SOMI_HIZ RW 0h

0h = SOMI line High-Z at bus idling time.

1h = SOMI line Pull down at bus idling time.

0 VDAC_MAPSW RW 0h 1h = Change channel assignments of DAC register (REG01~0A)

8.6.4.15 REG75 8-Bit Control Register for Parm1 (offset = 75h)

Figure 28. REG75 8-Bit Control Register for Parm1
7 6 5 4 3 2 1 0
TRAY_LOCKDET Reserved SPM_FAST
_BRK		 SPM_SLNT
_BRK		 SPM
_HIZMODE
rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. REG75 8-Bit Control Register for Parm1 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-5 TRAY_LOCKDET RW 0H

Load tray locking detection control

0h = Disable detection

1-7: Detection threshold

1h = 100 mA

2h = 150 mA

3h = 200 mA

4h = 250 mA

5h = 300 mA

6h = 350 mA

7h = 400 mA
4-3 Reserved RW 0h
2 SPM_FAST_BRK RW 0h

Fast brake mode selection

0h = Normal brake mode perform auto short brake sequence in specific speed

1h = No short brake under 5500 rpm

1 SPM_SLNT_BRK RW 0h

Silent brake mode selection

0h = Normal brake mode

1h = No active brake under 5500 rpm

Active brake mode is not performed inputting any value into VSPIN.

0 SPM_HIZMODE RW 0h

Spindle output Hi-Z mode

0h = Normal operation

1h = Spindle output (UVW) put Hi-Z (use for test purpose)

8.6.4.16 REG76 8-Bit Control Register for WriteEna (offset = 76h)

Figure 29. REG76 8-Bit Control Register for WriteEna
7 6 5 4 3 2 1 0
WRITE_ENABLE Reserved REG6X_Write Reserved
rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. REG76 8-Bit Control Register for WriteEna Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 WRITE_ENABLE RW 0h

0h = Register Write disable except REG76

1h = Write enable for registers REG01~09, REG70~7F

6-2 Reserved RW 0h
1 REG6X_Write RW 0h

0h = Disable Write access REG6X bank

1h = Enable Write access REG6X bank

8.6.4.17 REG77 8-Bit Control Register for ClrReg (offset = 77h)

Figure 30. REG77 8-Bit Control Register for ClrReg
7 6 5 4 3 2 1 0
RST_INDAC RST_REGS RST_ERR_FLAG Reserved
w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. REG77 8-Bit Control Register for ClrReg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 RST_INDAC W 0h

1h = Reset all 12-bit input DAC register (REG01~09)

*Self clear bit

6 RST_REGS W 0h

1h = Reset all 8-bit R/W registers (REG70h~77h, 60h-6Fh)

*Self clear bit

5 RST_ERR_FLAG W 0h

1h = Reset fault flag latch (REG7F, REG79~REG7D)

*Self clear bit

4-0 Reserved W 0h

8.6.4.18 REG78 8-Bit Control Register for ActTemp (offset = 78h)

Figure 31. REG78 8-Bit Control Register for ActTemp
7 6 5 4 3 2 1 0
Reserved ACT_TIMER
_PROT		 ACTTEMP
r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. REG78 8-Bit Control Register for ActTemp Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-6 Reserved R 0h
5 ACT_TIMER_PROT R 0h

ACT timer protection flag

1h = ACT Timer Protection has detected and latched.

(ACTTEMP > ACTTEMPTH)

This bit holds data after temperature change to low since this is a latch bit. Also driver output keep Hi-Z until setting RST_ERR_FLAG or ACTTEMPTH = 0.

4-0 ACTTEMP R 0h An integrated value of ACT_TIMER counters at present.

8.6.4.19 REG79 8-Bit Control Register for UVLOMon (offset = 79h)

Figure 32. REG79 8-Bit Control Register for UVLOMon
7 6 5 4 3 2 1 0
LIN9V_RDY RCD_BRK UVLO_P5V UVLO_INT3P3 UVLO_P12V UVLO_SIOV OVP_P5V OVP_P12V
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. REG79 8-Bit Control Register for UVLOMon Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 LIN9V_RDY R 0h LIN9V output status. LINFB voltage over 92% (typical) of target voltage.
6 RCD_BRK R 0h
5 UVLO_P5V R 0h UVLO flag for detection Low P5V supply (1)
4 UVLO_INT3P3 R 0h UVLO flag for detection Low internal 3.3-V regulator(1)
3 UVLO_P12V R 0h UVLO flag for detection Low P12V supply (1)
2 UVLO_SIOV R 0h UVLO flag for detection Low SIOV supply (1)
1 OVP_P5V R 0h OVP flag for P5V supply (1)
0 OVP_P12V R 0h OVP flag for P12V supply (1)
(1) Latched first reset event only. Cleared by RST_ERR_FLG (REG77)

8.6.4.20 REG7A 8-Bit Control Register for TSDMon (offset = 7Ah)

Figure 33. REG7A 8-Bit Control Register for TSDMon
7 6 5 4 3 2 1 0
Reserved TSD_FAULT
_SPM		 TSD_FAULT
_ACT		 TSD_FAULT
_P12DCHG		 Reserved TSD_SPM TSD_ACT TSD_ P12DCHG
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. REG7A 8-Bit Control Register for TSDMon Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R 0h
6 TSD_FAULT_SPM R 0h Prealert of thermal protection of Spindle block(1)
5 TSD_FAULT_ACT R 0h Prealert of thermal protection of focus /track /tilt sled1 /sled2 /step1 /step2 /load(1)
4 TSD_FAULT_P12DCHG R 0h Prealert of thermal protection of P12V discharge block (1)
3 Reserved R 0h
2 TSD_SPM R 0h

Thermal protection flag for spindle(1)

SPM output Hi-Z until temperature falls on release level

1h = Detect (latch)

1 TSD_ACT R 0h

Thermal protection flag for focus /track /tilt sled1 /sled2 /step1 /step2 /load(1)

Actuator output Hi-Z until temperature falls on release level

1h = Detect (latch)

0 TSD_ P12DCHG R 0h

Thermal protection flag for P12V discharge block(1)

IDCHG output Hi-Z until temperature falls on release level

1h = Detect (latch)

(1) Cleared by RST_ERR_FLAG bit (REG77)

8.6.4.21 REG7B 8-Bit Control Register for SCPMon (offset = 7Bh)

Figure 34. REG7B 8-Bit Control Register for SCPMon
7 6 5 4 3 2 1 0
Reserved SCP_SPM SCP_SLED SCP_LOAD SCP_ACT SCP_STP
r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. REG7B 8-Bit Control Register for SCPMon Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-5 Reserved R 0h
4 SCP_SPM R 0h Short protection flag bit for spindle block(1)
3 SCP_SLED R 0h Short protection flag bit for sled block(1)
2 SCP_LOAD R 0h Short protection flag bit for load block(1)
1 SCP_ACT R 0h Short protection flag bit for Actuator block(1)
0 SCP_STP R 0h Short protection flag bit for step block(1)
(1) Cleared by RST_ERR_FLAG bit (REG77)

8.6.4.22 REG7C 8-Bit Control Register for TempMon (offset = 7Ch)

Figure 35. REG7C 8-Bit Control Register for TempMon
7 6 5 4 3 2 1 0
CHIPTEMP
_STATUS		 CHIPTEMP
r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. REG7C 8-Bit Control Register for TempMon Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 CHIPTEMP_STATUS R 0h

1h = New data CHIPTEMP[6:0] is updated It will be cleared after reading.

6-0 CHIPTEMP R 0h

Chip temperature monitor (1.2°/LSB)

15° (0) to 165° (127)

For monitoring, TEMPMON_ENA = 1 and XSLEEP = 1 is required

8.6.4.23 REG7D 8-Bit Control Register for Status Monitor (offset = 7Dh)

Figure 36. REG7D 8-Bit Control Register for Status Monitor
7 6 5 4 3 2 1 0
SIF
_TIMEOUTERR		 XRSTIN_DET Reserved TRAY
_LOCKDETECT		 TRAY
_PUSHDETP		 TRAY
_PUSHDETN		 STP_ENDDET SLD_ENDDET
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. REG7D 8-Bit Control Register for Status Monitor Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 SIF_TIMEOUTERR R 0h

Error flag of serial I/F watch dog timer

1h = SIF communication was interrupted, expired watch dog timer

6 XRSTIN_DET R 0h

XRSTIN event flag

1h = Detect low event in XRSTIN pin

5 Reserved R 0h
4 TRAY_LOCKDETECT R 0h

TRAY lock detection flag

1h = Detect tray lock detection

3 TRAY_PUSHDETP R 0h

TRAY push event detection flag in LOAD_P pin

1h = Detect tray push event in LOAD_P pin

2 TRAY_PUSHDETN R 0h

TRAY push event detection flag in LOAD_N pin

1h = Detect tray push event in LOAD_N pin

1 STP_ENDDET R 0h

Step end event flag

1h = Detect step end event

0 SLD_ENDDET R 0h

Sled end event flag

1h = Detect sled end event

8.6.4.24 REG7E 8-Bit Control Register for Version (offset = 7Eh)

Figure 37. REG7E 8-Bit Control Register for Version
7 6 5 4 3 2 1 0
Version
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. REG7E 8-Bit Control Register for Version Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 Version R 0h

Version[7:4] = revision number of TPIC2060A

Version[3:0] = option

8.6.4.25 REG7F 8-Bit Control Register for Status (offset = 7Fh)

Figure 38. REG7F 8-Bit Control Register for Status
7 6 5 4 3 2 1 0
ACTTIMER
_FAULT		 MONITOR Reserved PWRERR TSDERR SCPERR TSDFAULT FG
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. REG7F 8-Bit Control Register for Status Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 ACTTIMER_FAULT R 0h

Status flag of ACTTIMER protection

1h = Prealert of ACTTIMER protection. It is close to the threshold level. The user can get current ACTTIMER value in REG78.

Both this bit and ACT_TIMER_PROT (REG78) will be set when over the threshold.

6 MONITOR R 0h

Event flag of any monitor event in REG7D

1h = Event occurred, details in REG7Dh

5 Reserved R 0h
4 PWRERR R 0h

Error flag of power

1h = Voltage problem occurred, details in REG79

3 TSDERR R 0h

Error flag of any overthermal protections

1h = Dispatched thermal protection, details in REG7A

2 SCPERR R 0h

Error flag of any SCP

1h = Dispatched SCP, details in REG7Bh

1 TSDFAULT R 0h

Warning of TSD of any thermal protection

1h = Detect pre-thermal protection, details in REG7A

0 FG R 0h FG signal. Spindle rotation pulse for speed monitor

8.6.4.26 REG60 8-Bit Control Register for SPMCfg (offset = 60h)

Figure 39. REG60 8-Bit Control Register for SPMCfg
7 6 5 4 3 2 1 0
Reserved FG_SBRK
_OFF		 Reserved IS_NZONE
_OFF		 Reserved
rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. REG60 8-Bit Control Register for SPMCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved RW 0h
6 FG_SBRK_OFF RW 0h FG Jitter setting in short brake period. Should be set to 1
5-2 Reserved RW 0h
1 IS_NZONE_OFF RW 0h Inductive position sense (IS) timing control. Should be set to 1
0 Reserved RW 0h

8.6.4.27 REG61 8-Bit Control Register for SPMCfg (offset = 61h)

Figure 40. REG61 8-Bit Control Register for SPMCfg
7 6 5 4 3 2 1 0
Reserved PWMmaxDuty
_R_SEL		 Reserved
rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. REG61 8-Bit Control Register for SPMCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-2 Reserved RW 0h
1 PWMmaxDuty_R_SEL RW 0h

PWM duty maximum setting in active brake mode

0h = Maximum PWM duty 12.5%

1h = Maximum PWM duty 25%

(Recommend to set 0 if using in no-disk because it may not stop in a specific motor setting 25%.)

0 Reserved RW 0h

8.6.4.28 REG62 8-Bit Control Register for SPMCfg (offset = 62h)

Figure 41. REG62 8-Bit Control Register for SPMCfg
7 6 5 4 3 2 1 0
Reserved TIME_BASE_SEL Reserved
rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. REG62 8-Bit Control Register for SPMCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-4 Reserved RW 0h
3-2 TIME_BASE_SEL RW 0h Spindle waveform selection. Should be set to 11
1-0 Reserved RW 0h

8.6.4.29 REG64 8-Bit Control Register for Protect (offset = 64h)

Figure 42. REG64 8-Bit Control Register for Protect
7 6 5 4 3 2 1 0
Reserved FG5M_OFF Reserved
rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. REG64 8-Bit Control Register for Protect Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-4 Reserved RW 0h
3 FG5M_OFF RW 0h Spindle FG filter selection. Should be set to 1
2-0 Reserved RW 0h

8.6.4.30 REG65 8-Bit Control Register for SPMCfg (offset = 65h)

Figure 43. REG65 8-Bit Control Register for SPMCfg
7 6 5 4 3 2 1 0
Reserved HZSVR_SEL Reserved
rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. REG65 8-Bit Control Register for SPMCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-5 Reserved RW 0h
4-3 HZSVR_SEL RW 0h Spindle waveform silent mode selection. Should be set to 11
2-0 Reserved RW 0h

8.6.4.31 REG68 8-Bit Control Register for Protect (offset = 68h)

Figure 44. REG68 8-Bit Control Register for Protect
7 6 5 4 3 2 1 0
Reserved SPM_TQAJST
rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. REG68 8-Bit Control Register for Protect Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-2 Reserved RW 0h
1-0 SPM_TQAJST RW 0h

Select fine adjust value of spindle limit current which is set by SPM_RCOM_SEL

00: No adjust

01: –5%

10: –10%

11: –15%

8.6.4.32 REG6B 8-Bit Control Register for DisProt (offset = 6Bh)

Figure 45. REG6B 8-Bit Control Register for DisProt
7 6 5 4 3 2 1 0
SCP_SPM
_OFF		 SCP_SLED
_OFF		 SCP_LOAD
_OFF		 SCP_ACT
_OFF		 SCP_STP_OFF SPM_RCDDIS Reserved
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. REG6B 8-Bit Control Register for DisProt Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 SCP_SPM_OFF RW 0h

Control bit of SCP function for spindle block.

0h = Enable SCP function

1h = Disable SCP function

Caution(1) TI recommends using it only for test purposes.

6 SCP_SLED_OFF RW 0h

For Sled driver block.

Caution(1) TI recommends using it only for test purposes.

5 SCP_LOAD_OFF RW 0h

For Load driver block

Caution(1) TI recommends using it only for test purposes.

4 SCP_ACT_OFF RW 0h

For Actuator driver block

Caution(1) TI recommends using it only for test purposes.

3 SCP_STP_OFF RW 0h

For Step driver block

Caution(1) TI recommends using it only for test purposes.

2 SPM_RCDDIS RW 0h

Spindle block reverse current detect function.

0h = Enable

1h = Disable

1-0 Reserved RW 0h
(1) Caution: Device will be fatally damaged if short circuit occurs in the xxx_OFF = 1.

8.6.4.33 REG6C 8-Bit Control Register for ENDCfg (offset = 6Ch)

Figure 46. REG6C 8-Bit Control Register for ENDCfg
7 6 5 4 3 2 1 0
PUSHDETTH PUSHDET_TIME Reserved
rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. REG6C 8-Bit Control Register for ENDCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-6 PUSHDETTH RW 0h

Detection voltage threshold for PUSH detection

00: Disable function

01: 1 V

10: 0.75 V

11: 0.5 V

5-4 PUSHDET_TIME RW 0h

Duration of PUSH detection

00: 104 ms

01: 208 ms

10: 416 ms

11: 0 ms (immediately at the exceeding threshold)

3-0 Reserved RW 0h

8.6.4.34 REG6E 8-Bit Control Register for UtilCfg (offset = 6Eh)

Figure 47. REG6E 8-Bit Control Register for UtilCfg
7 6 5 4 3 2 1 0
GPOUT_HL GPOUT_ENA Reserved
rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. REG6E 8-Bit Control Register for UtilCfg Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 GPOUT_HL RW 0h

General-purpose output (GPOUT) pin output selection

0h = Low output

1h = High output

Valid only if REG6F = 00h

6 GPOUT_ENA RW 0h

Enable monitor signal output to GPOUT pin

0h = No signal output, Hi-Z

1h = Output signal selected in REG6F with CMOS output

Output is logical OR when selected two more signals

5-0 Reserved RW 0h

8.6.4.35 REG6F 8-Bit Control Register for GPOUTSet (offset = 6Fh)

Figure 48. REG6F 8-Bit Control Register for GPOUTSet
7 6 5 4 3 2 1 0
ACTTIMER
_FLT_MON		 MONITOR
_MON		 Reserved PWRERR
_MON		 TSDERR_MON SCPERR_MON TSDFAULT
_MON		 SPMRCD
_BRK_MON
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. REG6F 8-Bit Control Register for GPOUTSet Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 ACTTIMER_FLT_MON RW 0h 1h = ACTTIMER fault output to GPOUT pin
6 MONITOR_MON RW 0h 1h = ENDDET monitor output to GPOUT pin
5 Reserved RW 0h
4 PWRERR_MON RW 0h 1h = PWRERR monitor output to GPOUT pin
3 TSDERR_MON RW 0h 1h = TSDERR fault output to GPOUT pin
2 SCPERR_MON RW 0h 1h = SCPERR fault output to GPOUT pin
1 TSDFAULT_MON RW 0h 1h = TSDFAULT fault output to GPOUT pin
0 SPMRCD_BRK_MON RW 0h 1h = SPMRCD_BRK fault output to GPOUT pin