SLIS166 July   2015 TPIC2060A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Serial I/F Write Timing Requirements
    7. 7.7 Serial I/F Read Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Functions
        1. 8.3.1.1 OVP
        2. 8.3.1.2 SCP
        3. 8.3.1.3 Temperature Shutdown (TSD)
        4. 8.3.1.4 ACTTIMER
    4. 8.4 Device Functional Modes
      1. 8.4.1 Differential Tilt Mode
      2. 8.4.2 Power-On Reset (POR)
        1. 8.4.2.1 RDY (Power Ready)
        2. 8.4.2.2 Voltage Monitoring
    5. 8.5 Programming
      1. 8.5.1 Serial Port Functional Description
      2. 8.5.2 Write Operation
      3. 8.5.3 Read Operation
      4. 8.5.4 Write and Read Operation
    6. 8.6 Register Maps
      1. 8.6.1 Register State Transition
      2. 8.6.2 DAC Register (12-Bit Write Only)
      3. 8.6.3 Control Register (8-Bit Read/Write)
      4. 8.6.4 Detailed Register Description
        1. 8.6.4.1  REG01 12-Bit DAC for Tilt (offset = 01h)
        2. 8.6.4.2  REG02 12-Bit DAC for Focus (offset = 02h)
        3. 8.6.4.3  REG03 12-Bit DAC for Tracking (offset = 03h)
        4. 8.6.4.4  REG04 12-Bit DAC for Sled1 (offset = 04h)
        5. 8.6.4.5  REG05 12-Bit DAC for Sled2 (offset = 05h)
        6. 8.6.4.6  REG06 12-Bit DAC for Stepping1 (offset = 06h)
        7. 8.6.4.7  REG07 12-Bit DAC for Stepping2 (offset = 07h)
        8. 8.6.4.8  REG08 12-Bit DAC for Spindle (offset = 08h)
        9. 8.6.4.9  REG09 12-Bit DAC for Load (offset = 09h)
        10. 8.6.4.10 REG70 8-Bit Control Register for DriverEna (offset = 70h)
        11. 8.6.4.11 REG71 8-Bit Control Register for FuncEna (offset = 71h)
        12. 8.6.4.12 REG72 8-Bit Control Register for ACTCfg (offset = 72h)
        13. 8.6.4.13 REG73 8-Bit Control Register for Parm0 (offset = 73h)
        14. 8.6.4.14 REG74 8-Bit Control Register for SIFCfg (offset = 74h)
        15. 8.6.4.15 REG75 8-Bit Control Register for Parm1 (offset = 75h)
        16. 8.6.4.16 REG76 8-Bit Control Register for WriteEna (offset = 76h)
        17. 8.6.4.17 REG77 8-Bit Control Register for ClrReg (offset = 77h)
        18. 8.6.4.18 REG78 8-Bit Control Register for ActTemp (offset = 78h)
        19. 8.6.4.19 REG79 8-Bit Control Register for UVLOMon (offset = 79h)
        20. 8.6.4.20 REG7A 8-Bit Control Register for TSDMon (offset = 7Ah)
        21. 8.6.4.21 REG7B 8-Bit Control Register for SCPMon (offset = 7Bh)
        22. 8.6.4.22 REG7C 8-Bit Control Register for TempMon (offset = 7Ch)
        23. 8.6.4.23 REG7D 8-Bit Control Register for Status Monitor (offset = 7Dh)
        24. 8.6.4.24 REG7E 8-Bit Control Register for Version (offset = 7Eh)
        25. 8.6.4.25 REG7F 8-Bit Control Register for Status (offset = 7Fh)
        26. 8.6.4.26 REG60 8-Bit Control Register for SPMCfg (offset = 60h)
        27. 8.6.4.27 REG61 8-Bit Control Register for SPMCfg (offset = 61h)
        28. 8.6.4.28 REG62 8-Bit Control Register for SPMCfg (offset = 62h)
        29. 8.6.4.29 REG64 8-Bit Control Register for Protect (offset = 64h)
        30. 8.6.4.30 REG65 8-Bit Control Register for SPMCfg (offset = 65h)
        31. 8.6.4.31 REG68 8-Bit Control Register for Protect (offset = 68h)
        32. 8.6.4.32 REG6B 8-Bit Control Register for DisProt (offset = 6Bh)
        33. 8.6.4.33 REG6C 8-Bit Control Register for ENDCfg (offset = 6Ch)
        34. 8.6.4.34 REG6E 8-Bit Control Register for UtilCfg (offset = 6Eh)
        35. 8.6.4.35 REG6F 8-Bit Control Register for GPOUTSet (offset = 6Fh)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  DAC Type
      2. 9.1.2  Example of 12-Bit DAC Sampling Rate for FCS/TRK/TLT
      3. 9.1.3  Digital Input Coding
      4. 9.1.4  Example Timing of Target Control System
      5. 9.1.5  Spindle Motor Driver Operating Sequence
      6. 9.1.6  Auto Short Brake Function
      7. 9.1.7  Spindle PWM Control
      8. 9.1.8  Spindle Driver Current Limit Circuit
      9. 9.1.9  Sled Driver Part
      10. 9.1.10 Stepping Driver Part
      11. 9.1.11 Focus/Track/Tilt Driver Part
        1. 9.1.11.1 Input VS Output Duty
      12. 9.1.12 Load Driver Part
      13. 9.1.13 End Detect Function
      14. 9.1.14 Load Tray Lock Detect Function
      15. 9.1.15 Load Tray Push Detect Function
      16. 9.1.16 Monitor Signal on GPOUT
      17. 9.1.17 9-V LDO
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (1)
MIN MAX UNIT
5-V supply voltage P5V 6 V
12-V supply voltage P12V 15
Load supply P5V12 voltage 15
Spindle output peak voltage 15
Spindle output current 2.5 A
Spindle output peak current、(PW ≤ 2 ms、Duty ≤ 30%) 3.5
Sled output peak current 1.0
Focus/tracking/tilt driver output peak current 1.0
Load driver output peak current 1.0
Input/output voltage –0.3 VCC + 0.3 V
Power dissipation (2) 1344 mW
Operating temperature –20 75 °C
Lead temperature 1.6 mm from case for 10 s 260
Tstg Storage temperature –60 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) A lower RθJC is attainable if the exposed pad is connected to a large copper ground plane. RθJC and RθJA are values for 56-pin TSSOP without a exposed heat slug (HSL) on bottom. 　Actual thermal resistance would be better than the above values.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Operating supply voltage (apply for P5V) 4.5 5.0 5.5 V
Driver 12-V supply voltage (apply for P12V)(1) 10.8 12.0 13.2
Load operating supply voltage (apply for P5V12L) 4.5 5.0 5.5
10.8 12.0 13.2
SIOV voltage 3.0 3.3 3.6
Operating temperature range –20 25 75 °C
SCLK frequency 30 33.8688 35 MHz
SIMO, SSZ, SCLK pin 'H' level input voltage range 2.2 SIOV + 0.2 V
SIMO, SSZ, SCLK pin 'L' level input voltage range –0.2 0.8
XRSTIN pin 'H' level input voltage 2.2 P5V + 0.1
XRSTIN pin 'L' level input voltage range –0.1 0.8
Spindle output current (U, V, W average total) 1.7 A
Spindle output current [peak] 3.0
Focus / tracking / tilt / loading / sled output current [average] 0.4
Focus / tracking / tilt / loading / sled output current [peak] 0.8
STP output average current 300 mA
(1) (P5V = 4.5 to 5.5 V, P12V = 10.8 to 13.2 V, CATA ≈ –20℃ to 75℃, unless otherwise noted)

7.4 Thermal Information

THERMAL METRIC(1) TPIC2060A UNIT
DFD (HTSSOP)
56 PINS
RθJA Junction-to-ambient thermal resistance 16.9 °C/W
RθJC Junction-to-case thermal resistance 0.8 °C/W
RθJB Junction-to-board thermal resistance 5.2 °C/W
ψJT Junction-to-top characterization parameter 1 °C/W
ψJB Junction-to-board characterization parameter 5.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PART
ISTBY Stand by supply current Standby mode (XSLEEP = 0) 0.6 1.2 mA
VCV3 CV3P3 output voltage Iload = 25 mA 3.1 3.3 3.5 V
RXM XRSTIN pulldown resistor 80 200 320 kΩ
RRDY RDY pullup resistor 13.2 33 52.8
VRDY RDY low level output voltage SIOV = 3.3 V, IOL = –100 µA 0.3 V
RXFG XFG output resistor 100 200 300 Ω
VXFGH XFG high-level output voltage SIOV = 3.3 V, XSLEEP = 1, IOH = 100 µA SIOV – 0.3 V
VSFGL XFG low-level output voltage SIOV = 3.3 V, XSLEEP = 1, IOL = -100 µA 0.3
RGPO GPOUT output resistor 100 200 300 Ω
VGPOH GPOUT high-level output voltage SIOV = 3.3 V, XSLEEP = 1, GPOUT_ENA = 1,GPOUT_HL = 1, IOH = 100 µA SIOV – 0.3 V
VGPOL GPOUT low-level output voltage SIOV = 3.3 V, XSLEEP = 1, GPOUT_ENA = 1,GPOUT_HL = 0, IOH = 100 µA 0.3 V
TTSD Thermal protection on temperature Design value 135 150 165 °C
TTSDhys Thermal protection hysteresis temperature 5 15 25
Vonvcc P5V reset on voltage 3.6 3.7 3.8 V
Voffvcc P5V reset off voltage 3.6 3.8 4.0
Vonvcc P12V reset on voltage 7.9 8.4 8.9
Voffvcc P12V reset off voltage 8.3 8.8 9.3
VonCV3 CV3P3 reset on voltage 2.55 2.7 2.85
VoffCV3 CV3P3 reset off voltage 2,65 2,8 2,95
VonSIOV SIOV reset on voltage (1) 1.9 2 2.1
VoffSIOV SIOV reset off voltage (1) 2 2.1 2.2
VovpspmOn OVP detection voltage (spindle)(1) 14.2 14.9 15.6
VovpspmOff OVP release voltage (spindle)(1) 13.8 14.5 15.2
VovpOn OVP detection voltage (except spindle) (1) 5.9 6.2 6.5
VovpOff OVP release voltage (except spindle) (1) 5.7 6.0 6.3
CHARGE PUMP PART
FCHGP Frequency XSLEEP = 1 132.6 156 179.4 kHz
VCHGP Output voltage Ccp1 = Ccp3 = 0.1 µF Io = –1 mA 15.6 18.5 21.4 V
SPINDLE MOTOR DRIVER PART
RttlSPM Total output resistance high side + low side IOUT = 500 mA 0.4 0.7 Ω
ResSPM Resolution 12 bit
VoutSPM Spindle grain Magnification to 1.0 inputs 12.4 14.0 15.6 times
WidDZSPM Spindle dead band Forward 12h 52h 92h
Reverse –92h –52h –12h
SPMClim Current limit SPM_RCOM_SEL = 00
SPM_TQAJST = 00 		1019.7 1133 1246.3 mA
SPM_RCOM_SEL = 01
SPM_TQAJST = 00 		694.8 772 849.2
SPM_RCOM_SEL = 10
SPM_TQAJST = 00 		1274.4 1416 1557.6
SPM_RCOM_SEL = 11
SPM_TQAJST = 00 		1530.0 1700 1870.0
SPMClimF Current limit fine adjust SPM_RCOM_SEL = xx
SPM_TQAJST = 01 		–4% –5% –6%
SPM_RCOM_SEL = xx
SPM_TQAJST = 10 		–8% –10% –12%
SPM_RCOM_SEL = xx
SPM_TQAJST = 11 		–12% –15% –18%
SLED MOTOR DRIVER PART
RttlSLD Total output resistance high side + low side P12 V = 10.8 to 13.2 V, IO = 500 mA 1.6 2.5 Ω
ResSLD Resolution 10 bit
WidDZSLD input dead band Forward +1Fh
Reverse –20h
GnSLD Sled current gain P5V = 5 V,P12V = 12 V VSLED = 7FFh 760 880 1000 mA
VthEdetSLD END_DET BEMF threshold voltage SLD_ENA = 1, SLD_ENDDET_ENA = 1, SLEDENDTH <1:0> = 00 62 124 186 mV
SLEDENDTH<1:0> = 01 35 72 105
SLEDENDTH<1:0> = 11 80 168 250
FOCUS/TILT/TRACKING DRIVER PART
RttlAct Each channel total output resistance high side + low side P5V = 4.5 to 5.5 V、IO = 500 mA 0.7 1.1 Ω
ResACT Resolution 12 bit
VOfstACT Each channel output offset voltage DAC_code = 000h –20 0 20 mV
GnAct Each channel voltage gain Magnification to 1.0 inputs 5 6 7 times
DifOff FCS, TLT differential output offset voltage DIFF_TLT = 1, FCS-TLT –40 0 40 mV
GnDAct FCS, TLT differential gain ratio DIFF_TLT = 1, FCS-TLT (Typ = 1) 0.89 1 1.13
LOAD DRIVER PART
RttlLOD Total output resistance high side + low side P5V12L = 4.5 V to 5.5 V、IO = 500 mA 1.2 1.9 Ω
P5V12L = 10.8 V to 13.2 V、IO = 500 mA
ResLOD Resolution 12 bit
GnLOD Voltage gain P5V12L = 4.5 to 5.5 V 5.1 6.0 6.9 times
P5V12L = 10.8 to 13.2 V 12.6 14.0 15.4
WidDZLOD Dead band Forward 20h
Reverse –21h
LockDth Tray lock detect threshold current P5V12L = 5 V, TRAY_LOCKDET[2:0] = 1 80 100 120 mA
P5V12L = 12 V, TRAY_LOCKDET[2:0] = 1 80 100 120
P5V12L = 5 V, TRAY_LOCKDET[2:0] = 2 120 150 180
P5V12L = 12 V, TRAY_LOCKDET[2:0] = 2 120 150 180
P5V12L = 5 V, TRAY_LOCKDET[2:0] = 3 160 200 240
P5V12L = 12 V, TRAY_LOCKDET[2:0] = 3 160 200 240
P5V12L = 5 V, TRAY_LOCKDET[2:0] = 4 212 250 287
P5V12L = 12 V, TRAY_LOCKDET[2:0] = 4 212 250 287
P5V12L = 5 V, TRAY_LOCKDET[2:0] = 5 255 300 345
P5V12L = 12 V, TRAY_LOCKDET[2:0] = 5 255 300 345
P5V12L = 5 V, TRAY_LOCKDET[2:0] = 6 297 350 402
P5V12L = 12 V, TRAY_LOCKDET[2:0] = 6 297 350 402
P5V12L = 5 V, TRAY_LOCKDET[2:0] = 7 340 400 460
P5V12L = 12 V, TRAY_LOCKDET[2:0] = 7 340 400 460
PushDVth Tray push detect voltage threshold LOAD_ENA = 0, P5V12L = 12V, PUSHDETTH[1:0] = 01 0.8 1.0 1.2 V
LOAD_ENA = 0, P5V12L = 12V, PUSHDETTH[1:0] = 10 0.52 0.75 0.96
LOAD_ENA = 0, P5V12L = 12V, PUSHDETTH[1:0] = 11 0.27 0.5 0.63
PushDTth Tray push detect time threshold LOAD_ENA = 0, P5V12L = 12V, PUSHDETTH_TIME[1:0] = 00 78 104 130 ms
LOAD_ENA = 0, P5V12L = 12V, PUSHDETTH_TIME[1:0] = 01 156 208 260
LOAD_ENA = 0, P5V12L = 12V, PUSHDETTH_TIME[1:0] = 10 312 416 520
LOAD_ENA = 0, P5V12L = 12V, PUSHDETTH_TIME[1:0] = 11 0 25
STEPPING MOTOR DRIVER PART
RttlSTP Total output resistance high side + low side IO = 100 mA 1.0 1.5 Ω
ResSTP Resolution 8 bit
VthEdetSTP END_DET threshold level STP_ENA = 1, STP_ENDDET_ENA = 1, STPDENDTH<1:0> = 00 19 39 59 mV
9-V LDO DRIVER PART
LINFBVth LINFB threshold voltage 1.165 1.215 1.265 V
THERMOMETER PART
ResTEMP Resolution 7 bit
Trng Temperature range CHIPTEMP[6:0] = 00 8 15 22 °C
CHIPTEMP[6:0] = 7Fh 155 165 175
FTEMP Update cycle 10 kHz
ACTUATOR PROTECTION
tintACTTEMP Update cycle 26 ms
SERIAL PORT VOLTAGE LEVELS
SOMI High-level output voltage, VOH IOH = 1 mA 80% SIOV V
SOMI Low-level output voltage, VOL IOL = 1 mA 20% SIOV
SIMO High-level input voltage, VIH 70% SIOV
SIMO Low level input voltage, VIL 20% SIOV
tSIMO Input rise/fall time 20% to 80% of SIOV 3.5 ns
tSOMI Output rise/fall time Cload = 30 pF, 20% to 80% of SIOV 10
RSCLK Internal pulldown resistance 80 200 320 kΩ
RSSZ Internal pullup resistance 80 200 320
RSIMO Internal pulldown resistance 80 200 320
(1) These values are protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause permanent damage to the device.

7.6 Serial I/F Write Timing Requirements

MIN NOM MAX UNIT
ƒck SCLK clock frequency (SIOV = 3.3 V) 35 MHz
tckl SCLK low time 11 ns
tckh SCLK high time 11 ns
tsens SSZ setup time 7 ns
tsenh SSZ hold time 7 ns
tsl SSZ disable high time 11 ns
tds SIMO setup time (Write) 7 ns
tdh SIMO hold time (Write) 7 ns
TPIC2060A slis166_serial_write_timing.gif Figure 1. Serial Port Write Timing

7.7 Serial I/F Read Timing Requirements

MIN NOM MAX UNIT
ƒck SCLK clock frequency (SIOV = 3.3 V) 35 MHz
tckl SCLK low time 11 ns
tckh SCLK high time 11 ns
tsens SSZ setup time 7 ns
tsenh SSZ hold time 7 ns
tsl SSZ disable high time 11 ns
tds SIMO setup time (Write) 7 ns
tdh SIMO hold time (Write) 7 ns
trdly SOMI delay time (Read) - (CLOAD = 10 pF, SIOV = 3.3 V) 2 9 ns
tsendl SOMI hold time (Read) - (CLOAD = 10 pF, SIOV = 3.3 V) 2 9 ns
trls SOMI release time (Read) - (CLOAD = 10 pF, SIOV = 3.3 V) From SSZ rise to SOMI HIZ 0 9 ns
TPIC2060A slis166_serial_read_timing.gif Figure 2. Serial Port Read Timings
TPIC2060A slis166_serial_read_timing_adv.gif Figure 3. Serial Port Read Timings (Advanced Read Mode)

7.8 Typical Characteristics

TPIC2060A D003_SLIS166.gif Figure 4. STP1 Driver: DAC Code vs Output On Duty
TPIC2060A D004_SLIS166.gif Figure 5. STP2 Driver: DAC Code vs Output On Duty