SLIS134C March   2011  – September 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Voltage Divider Mode
      3. 7.4.3 Rheostat Mode
    5. 7.5 Programming with I2C
      1. 7.5.1 I2C General Operation
        1. 7.5.1.1 I2C Interface
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Data Validity and Byte Formation
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      2. 7.5.2 I2C Write and Read Operation
        1. 7.5.2.1 Auto Increment Function
        2. 7.5.2.2 Write Operation
        3. 7.5.2.3 Repeated Start
        4. 7.5.2.4 Read Operation
    6. 7.6 Register Maps
      1. 7.6.1 Slave Address
      2. 7.6.2 TPL0102 Register Map
      3. 7.6.3 IVRA (Initial Value Register for Potentiometer A)
      4. 7.6.4 WRA (Wiper Resistance Register for Potentiometer A)
      5. 7.6.5 IVRB (Initial Value Register for Potentiometer B)
      6. 7.6.6 WRB (Wiper Resistance Register for Potentiometer B)
      7. 7.6.7 ACR (Access Control Register)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Adjustable Gain Non-Inverting Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Digital to Analog Converter (DAC)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Variable Current Sink
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Compensation Components
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequence
    2. 9.2 Wiper Position Upon Power Up
    3. 9.3 Dual-Supply vs Single-Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

To ensure reliability of the device, please follow common printed-circuit board layout guidelines.

  • Leads to the input should be as direct as possible with a minimum conductor length.
  • The ground path should have low resistance and low inductance.
  • Short trace-lengths should be used to avoid excessive loading.
  • It is common to have a dedicated ground plane on an inner layer of the board.
  • Terminals that are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours and multiple vias.
  • Bypass capacitors should be used on power supplies and should be placed as close as possible to the VDD and VSS pins.
  • Apply low equivalent series resistance 0.1 µF to 10 µF tantalum or electrolytic capacitors at the supplies to minimize transient disturbances and to filter low frequency ripple.
  • To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCL and SDA) should be a short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper weight).

10.2 Layout Example

TPL0102 layout_slis134.gif Figure 37. TPL0102 Layout Example