Figure 8-18 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses a strong 3.7-A peak source and 4-A peak sink gate drivers. The strong gate drivers enable paralleling of FETs in high power system designs ensuring minimum transition time in saturation region. A 12-V, 100-µA charge pump is derived from VS terminal and charges the external boot-strap capacitor, C_BST that is placed across the gate driver (BST and SRC).

In switching applications, if the charge pump supply demand is higher than 100 µA, then supply BST externally using a low leakage diode and V_AUX supply as shown in the Figure 8-18.

VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and charges the C_BST capacitor. After the voltage across C_BST crosses V_{(BST_UVLOR)}, the GATE driver section is activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial GATE turn ON. Choose C_BST based on the external FET QG and allowed dip during FET turn-ON. The charge pump remains enabled until the BST to SRC voltage reaches 12.3 V, typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC voltage discharges to 11.7 V typically at which point the charge pump is enabled. The voltage between BST and SRC continue to charge and discharge between 12.3 V and 11.7 V as shown in the Figure 8-18.

Use the following equation to calculate the initial gate driver enable delay.

Where,

C_BST is the charge pump capacitance connected across BST and SRC pins.

V_{(BST_UVLOR)} = 7.6 V (typical).

If T_{DRV_EN} must be reduced, then pre-bias the BST terminal externally using an external V_AUX supply through a low leakage diode D₁ as shown in Figure 8-18. With this connection, T_{DRV_EN} reduces to 350 µs. TPS1211x-Q1 application circuit with external sypply to BST is shown in Figure 8-5.