SLVS514M June   2010  – June 2016 TPS2041B , TPS2042B , TPS2043B , TPS2044B , TPS2051B , TPS2052B , TPS2053B , TPS2054B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. General Switch Catalog
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Power Switch
      2. 9.3.2 Charge Pump
      3. 9.3.3 Driver
      4. 9.3.4 Enable (ENx)
      5. 9.3.5 Enable (ENx)
      6. 9.3.6 Overcurrent (OCx)
      7. 9.3.7 Current Sense
      8. 9.3.8 Thermal Sense
      9. 9.3.9 Undervoltage Lockout
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Universal Serial Bus (USB) Applications
    2. 10.2 Typical Application
      1. 10.2.1 Typical Application (TPS2042B)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Power-Supply Considerations
          2. 10.2.1.2.2 Overcurrent
          3. 10.2.1.2.3 OC Response
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Host and Self-Powered and Bus-Powered Hubs
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 USB Power-Distribution Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Low-Power Bus-Powered and High-Power Bus-Powered Functions
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Generic Hot-Plug Applications
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Undervoltage Lockout (UVLO)
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation
    4. 12.4 Thermal Protection
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Universal Serial Bus (USB) Applications

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (for example, keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply.

The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements:

  • Hosts and self-powered hubs (SPH)
  • Bus-powered hubs (BPH)
  • Low-power, bus-powered functions
  • High-power, bus-powered functions
  • Self-powered functions

Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS20xxB can provide power-distribution solutions to many of these classes of devices.

Typical Application

Typical Application (TPS2042B)

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ai_typ_cir_lvs514.gif Figure 32. Typical Application (Example, TPS2042B)

Design Requirements

Table 1 shows the design parameters for this application.

Table 1. Design Parameters

DESIGN PARAMETER VALUE
Input voltage 5 V
Output1 voltage 5 V
Output2 voltage 5 V
Output1 current 0.5 A
Output2 current 0.5 A

Detailed Design Procedure

Power-Supply Considerations

TI recommends placing a 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device. When the output load is heavy, TI recommends placing a high-value electrolytic capacitor on the necessary output pins. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.

Overcurrent

A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 23 through Figure 26). The TPS20xxB senses the short and immediately switches into a constant-current output.

In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.

In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 9 through Figure 12). The TPS20xxB is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.

OC Response

The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS20xxB is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown.

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ai_pin_app_lvs514.gif Figure 33. Typical Circuit for the OC Pin (Example, TPS2042B)

Application Curves

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl_ris_tm_lvs514.gif
Figure 34. Turnon Delay and Rise Time With 1-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl2_ris_tm_lvs514.gif
Figure 36. Turnon Delay and Rise Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B sh-cir_to_sh_lvs514.gif
Figure 38. Short-Circuit Current,
Device Enabled Into Short
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm3_endev_lvs514.gif
Figure 40. 3-Ω Load Connected to Enabled Device
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl_fal_tm_lvs514.gif
Figure 35. Turnoff Delay and Fall Time With 1-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl2_fal_tm_lvs514.gif
Figure 37. Turnoff Delay and Fall Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icur_lcap_lvs514.gif
Figure 39. Inrush Current With Different
Load Capacitance
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm2_endev_lvs514.gif
Figure 41. 2-Ω Load Connected to Enabled Device

Host and Self-Powered and Bus-Powered Hubs

Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports (see Figure 42 and Figure 43). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ai_one_port_lvs514.gif Figure 42. Typical One-Port USB Host and Self-Powered Hub
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ai_four_port_lvs514.gif Figure 43. Typical Four-Port USB Host and Self-Powered Hub

Design Requirements

USB Power-Distribution Requirements

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented.

  • Hosts and self-powered hubs must:
    • Current-limit downstream ports
    • Report overcurrent conditions on USB VBUS
  • Bus-powered hubs must:
    • Enable/disable power to downstream ports
    • Power up at <100 mA
    • Limit inrush current (<44 Ω and 10 µF)
  • Functions must:
    • Limit inrush currents
    • Power up at <100 mA

The feature set of the TPS20xxB allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 44 through Figure 47).

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B hybrid_41b_lvs514.gif Figure 44. Hybrid Self and Bus-Powered Hub Implementation, TPS2041B and TPS2051B
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ai_hybrid_lvs514.gif Figure 45. Hybrid Self and Bus-Powered Hub Implementation, TPS2042B and TPS2052B
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B hybrid_53b_lvs514.gif Figure 46. Hybrid Self and Bus-Powered Hub Implementation, TPS2043B and TPS2053B
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B hybrid_44b_lvs514.gif Figure 47. Hybrid Self and Bus-Powered Hub Implementation, TPS2044B and TPS2054B

Detailed Design Procedure

Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

Low-Power Bus-Powered and High-Power Bus-Powered Functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 μF at power up, the device must implement inrush current limiting (see Figure 48).

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ai_high_pwr_lvs514.gif Figure 48. High-Power Bus-Powered Function (Example, TPS2042B)

Application Curves

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl_ris_tm_lvs514.gif
Figure 49. Turnon Delay and Rise Time With 1-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl2_ris_tm_lvs514.gif
Figure 51. Turnon Delay and Rise Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B sh-cir_to_sh_lvs514.gif
Figure 53. Short-Circuit Current,
Device Enabled Into Short
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm3_endev_lvs514.gif
Figure 55. 3-Ω Load Connected to Enabled Device
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl_fal_tm_lvs514.gif
Figure 50. Turnoff Delay and Fall Time with 1-μF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl2_fal_tm_lvs514.gif
Figure 52. Turnoff Delay and Fall Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icur_lcap_lvs514.gif
Figure 54. Inrush Current With Different
Load Capacitance
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm2_endev_lvs514.gif
Figure 56. 2-Ω Load Connected to Enabled Device

Generic Hot-Plug Applications

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS20xxB, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS20xxB also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module.

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ai_hot_plug_lvs514.gif Figure 57. Typical Hot-Plug Implementation (Example, TPS2042B)

By placing the TPS20xxB between the VCC input and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device.

Design Requirements

Table 2 shows the design parameters for this application.

Table 2. Design Parameters

DESIGN PARAMETER VALUE
Input voltage 5 V
Output1 voltage 5 V
Output2 voltage 5 V
Output1 current 0.5 A
Output2 current 0.5 A

Detailed Design Procedure

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

  • Normal Input Operation Voltage
  • Current Limit

Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, as close to the device as possible for local noise decoupling. This precaution reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the input to reduce voltage undershoot from exceeding the UVLO of other load share one power rail with TPS2042 device or overshoot from exceeding the absolute-maximum voltage of the device during heavy transient conditions. This is especially important during bench testing when long, inductive cables are used to connect the evaluation board to the bench power supply. Output capacitance is not required, but TI recommends placing a high-value electrolytic capacitor on the output pin when large transient currents are expected on the output to reduce the undershoot, which is caused by the inductance of the output power bus just after a short has occurred and the TPS2042 device has abruptly reduced OUT current. Energy stored in the inductance will drive the OUT voltage down and potentially negative as it discharges.

Application Curves

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl_ris_tm_lvs514.gif
Figure 58. Turnon Delay and Rise Time With 1-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl2_ris_tm_lvs514.gif
Figure 60. Turnon Delay and Rise Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B sh-cir_to_sh_lvs514.gif
Figure 62. Short-Circuit Current,
Device Enabled Into Short
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm3_endev_lvs514.gif
Figure 64. 3-Ω Load Connected to Enabled Device
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl_fal_tm_lvs514.gif
Figure 59. Turnoff Delay and Fall Time With 1-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl2_fal_tm_lvs514.gif
Figure 61. Turnoff Delay and Fall Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icur_lcap_lvs514.gif
Figure 63. Inrush Current With Different
Load Capacitance
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm2_endev_lvs514.gif
Figure 65. 2-Ω Load Connected to Enabled Device