SLVS514M June   2010  – June 2016 TPS2041B , TPS2042B , TPS2043B , TPS2044B , TPS2051B , TPS2052B , TPS2053B , TPS2054B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. General Switch Catalog
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Power Switch
      2. 9.3.2 Charge Pump
      3. 9.3.3 Driver
      4. 9.3.4 Enable (ENx)
      5. 9.3.5 Enable (ENx)
      6. 9.3.6 Overcurrent (OCx)
      7. 9.3.7 Current Sense
      8. 9.3.8 Thermal Sense
      9. 9.3.9 Undervoltage Lockout
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Universal Serial Bus (USB) Applications
    2. 10.2 Typical Application
      1. 10.2.1 Typical Application (TPS2042B)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Power-Supply Considerations
          2. 10.2.1.2.2 Overcurrent
          3. 10.2.1.2.3 OC Response
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Host and Self-Powered and Bus-Powered Hubs
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 USB Power-Distribution Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Low-Power Bus-Powered and High-Power Bus-Powered Functions
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Generic Hot-Plug Applications
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Undervoltage Lockout (UVLO)
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation
    4. 12.4 Thermal Protection
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VI(IN), VI(INx) Input voltage (2) –0.3 6 V
VO(OUT), VO(OUTx)(2) Output voltage –0.3 6 V
VI(EN), VI(ENx), VI(EN), VI(ENx) Input voltage –0.3 6 V
VI(/OC), VI(OCx) Voltage range –0.3 6 V
IO(OUT), IO(OUTx) Continuous output current Internally limited
Continuous total power dissipation See Dissipation Ratings
TJ Operating virtual junction temperature –40 125 °C
Tstg Storage temperature –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI(IN), VI(INx) Input voltage 2.7 5.5 V
VI(EN), VI(ENx), VI(EN), VI(ENx) Input voltage 0 5.5 V
IO(OUT), IO(OUTx) Continuous output current 0 500 mA
TJ Operating virtual junction temperature –40 125 °C

Thermal Information

THERMAL METRIC(1) TPS2042xx and TPS2053xx UNIT
D
(SOIC)
DBV
(SOT-23)
DGN
(HVSSOP)
DRB
(SON)
8 PINS 16 PINS 5 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 119.3 81.6 208.6 53.6 47.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 67.6 42.7 122.9 58.7 53 °C/W
RθJB Junction-to-board thermal resistance 59.6 39.1 37.8 35.5 14.2 °C/W
ψJT Junction-to-top characterization parameter 20.3 10.4 14.6 2.7 1.2 °C/W
ψJB Junction-to-board characterization parameter 59.1 38.8 36.9 35.3 14.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A 6.7 7.3 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(/ENx) = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
POWER SWITCH
rDS(on) Static drain-source on-state resistance, 5-V operation and 3.3-V operation VI(IN) = 5 V or 3.3 V, IO = 0.5 A,
-40°C ≤ TJ ≤ 125°C
D and DGN packages 70 135
DBV package only 95 140
Static drain-source on-state resistance, 2.7-V operation VI(IN) = 2.7 V, IO = 0.5 A,
–40°C ≤ TJ ≤ 125°C
D and DGN packages 75 150
Static drain-source on-state resistance, 5-V operation VI(IN) = 5 V, IO = 1 A, OUT1 and OUT2
connected, 0°C ≤ TJ ≤ 70°C
DGN package, TPS2042B/52B 49
tr Rise time, output VI(IN) = 5.5 V CL = 1 μF,
RL = 10 Ω
TJ = 25°C 0.6 1.5 ms
VI(IN) = 2.7 V 0.4 1
tf Fall time, output VI(IN) = 5.5 V 0.05 0.5
VI(IN) = 2.7 V 0.05 0.5
ENABLE INPUT EN AND ENx
VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 V
VIL Low-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 0.8
II Input current VI(ENx) = 0 V or 5.5 V –0.5 0.5 μA
ton Turnon time CL = 100 μF, RL = 10 Ω 3 ms
toff Turnoff time CL = 100 μF, RL = 10 Ω 10
CURRENT LIMIT
IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
TJ = 25°C 0.75 1 1.25 A
–40°C ≤ TJ ≤ 125°C 0.7 1 1.3
VI(IN) = 5 V, OUT1 and OUT2 connected to
GND, device enabled into short-circuit, measure at IN
0°C ≤ TJ ≤ 70°C
TPS2042B/52B
1.5
IOC Overcurrent trip threshold VIN = 5 V, 100 A/s TPS2041B/51B IOS 1.5 1.9 A
TPS2042B/52B IOS 1.55 2
SUPPLY CURRENT (TPS2041B, TPS2051B)
Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C 0.5 1 μA
-40°°C ≤ TJ ≤ 125°C 0.5 5
Supply current, high-level output No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C 43 60 μA
–40°C ≤ TJ ≤ 125°C 43 70
Leakage current OUT connected to ground, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
–40°C ≤ TJ ≤ 125°C 1 μA
Reverse leakage current VI(OUTx) = 5.5 V, IN = ground TJ = 25°C 0 μA
SUPPLY CURRENT (TPS2042B, TPS2052B)
Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V TJ = 25°C 0.5 1 μA
–40°C ≤ TJ ≤ 125°C 0.5 5
Supply current, high-level output No load on OUT, VI(ENx) = 0 V TJ = 25°C 50 70 μA
–40°C ≤ TJ ≤ 125°C 50 90
Leakage current OUT connected to ground, VI(ENx) = 5.5 V –40°C ≤ TJ ≤ 125°C 1 μA
Reverse leakage current VI(OUTx) = 5.5 V, IN = ground TJ = 25°C 0.2 μA
SUPPLY CURRENT (TPS2043B, TPS2053B)
Supply current, low-level output No load on OUT, VI(ENx) = 0 V TJ = 25°C 0.5 2 μA
–40°C ≤ TJ ≤ 125°C 0.5 10
Supply current, high-level output No load on OUT, VI(ENx) = 5.5 V TJ = 25°C 65 90 μA
–40°C ≤ TJ ≤ 125°C 65 110
Leakage current OUT connected to ground, VI(ENx) = 0 V –40°C≤ TJ ≤ 125°C 1 μA
Reverse leakage current VI(OUTx) = 5.5 V, INx = ground TJ = 25°C 0.2 μA
SUPPLY CURRENT (TPS2044B, TPS2054B)
Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C 0.5 2 μA
–40°C ≤ TJ ≤ 125°C 0.5 10
Supply current, high-level output No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C 75 110 μA
–40°C ≤ TJ ≤ 125°C 75 140
Leakage current OUT connected to ground, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
–40°C≤ TJ ≤ 125°C 1 μA
Reverse leakage current VI(OUTx) = 5.5 V, INx = ground TJ = 25°C 0.2 μA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN, INx 2 2.5 V
Hysteresis, IN, INx TJ = 25°C 75 mV
OVERCURRENT OC and OCx
Output low voltage, VOL(/OCx) IO(OCx) = 5 mA 0.4 V
Off-state current VO(OCx) = 5 V or 3.3 V 1 μA
OC deglitch OCx assertion or deassertion 4 8 15 ms
THERMAL SHUTDOWN(2)
Thermal shutdown threshold 135 °C
Recovery from thermal shutdown 125 °C
Hysteresis 10 °C
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
The thermal shutdown only reacts under overcurrent conditions.

Dissipation Ratings

PACKAGE THERMAL RESISTANCE, θJA TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGN-8 1712.3 mW 17.123 mW/°C 941.78 mW 684.93 mW
D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW
D-16 898.47 mW 8.9847 mW/°C 494.15 mW 359.38 mW
DBV-5 285 mW 2.85 mW/°C 155 mW 114 mW
DRB-8 (Low-K)(1) 270 °CW 370 mW 3.71 mW/°C 203 mW 148 mW
DRB-8 (High-K)(2) 60 °CW 1600 mW 16.67 mW/°C 916 mW 866 mW
Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details.
Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details.

Typical Characteristics

TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B tontim_v_vi_lvs514.gif
Figure 1. Turnon Time vs Input Voltage
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ristim_v_vi_lvs514.gif
Figure 3. Rise Time vs Input Voltage
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc_41b_tj_lvs514.gif
Figure 5. TPS2041B and TPS2051B Supply Current, Output Enabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc_53b_tj_lvs514.gif
Figure 7. TPS2043B and TPS2053B Supply Current, Output Enabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc2_41b_tj_lvs514.gif
Figure 9. TPS2041B TPS2051B Supply Current, Output Disabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc2_53b_tj_lvs514.gif
Figure 11. TPS2043B and TPS2053B Supply Current, Output Disabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B rdson_44b_tj_lvs514.gif
Figure 13. Static Drain-Source on-State Resistance vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B thrcur_v_vi_lvs514.gif
Figure 15. Threshold Trip Current vs Input Voltage
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B uvlo_41b_tj_lvs514.gif
Figure 17. Undervoltage Lockout vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl_ris_tm_lvs514.gif
Figure 19. Turnon Delay and Rise Time With 1-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ondl2_ris_tm_lvs514.gif
Figure 21. Turnon Delay and Rise Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B sh-cir_to_sh_lvs514.gif
Figure 23. Short-Circuit Current,
Device Enabled Into Short
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm3_endev_lvs514.gif
Figure 25. 3-Ω Load Connected to Enabled Device
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B tofftim_44b_lvs514.gif
Figure 2. Turnoff Time vs Input Voltage
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B faltim_v_vi_lvs514.gif
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Figure 4. Fall Time vs Input Voltage
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc_v_tj_lvs490.gif
Figure 6. TPS2042B and TPS2052B Supply Current, Output Enabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc_44b_tj_lvs514.gif
Figure 8. TPS2044B TPS2054B Supply Current, Output Enabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc2_v_tj_lvs490.gif
Figure 10. TPS2042B and TPS2052B Supply Current, Output Disabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icc2_44b_tj_lvs514.gif
Figure 12. TPS2044B and TPS2054B Supply Current, Output Disabled vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B scios_v_tj_lvs514.gif
Figure 14. Short-Circuit Output Current vs Junction Temperature
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B thrcurr_2_vi_lvs514.gif
Figure 16. Threshold Trip Current vs Input Voltage
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ttcur_44b_pk_lvs514.gif
Figure 18. Current-Limit Response vs Peak Current
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl_fal_tm_lvs514.gif
Figure 20. Turnoff Delay and Fall Time With 1-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ofdl2_fal_tm_lvs514.gif
Figure 22. Turnoff Delay and Fall Time With 100-µF Load
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B icur_lcap_lvs514.gif
Figure 24. Inrush Current With Different
Load Capacitance
TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B ohm2_endev_lvs514.gif
Figure 26. 2-Ω Load Connected to Enabled Device