SLVSAU6H June   2011  – April 2016 TPS2000C , TPS2001C , TPS2041C , TPS2051C , TPS2061C , TPS2065C , TPS2065C-2 , TPS2068C , TPS2069C , TPS2069C-2

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: SOT-23
    5. 7.5 Thermal Information: MSOP-PowerPAD
    6. 7.6 Electrical Characteristics: TJ = TA = 25°C
    7. 7.7 Electrical Characteristics: -40°C ≤ TJ ≤ 125°C
    8. 7.8 Timing Requirements: TJ = TA = 25°C
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout
      2. 8.3.2 Enable
      3. 8.3.3 Internal Charge Pump
      4. 8.3.4 Current Limit
      5. 8.3.5 FLT
      6. 8.3.6 Output Discharge
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitance
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS20xxC and TPS20xxC-2 current-limited power switch uses N-channel MOSFETs in applications requiring continuous load current. The device enters constant-current mode when the load exceeds the current limit threshold.

9.2 Typical Application

TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 Typical_application_schematic.gif Figure 23. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the following input parameters:

  1. The TPS2065CDGN operates from a 5-V to ±0.5-V input rail.
  2. What is the normal operation current, for example, the maximum allowable current drawn by portable equipment for USB 3.0 port is 900 mA, so the normal operation current is 900 mA, and the minimum current limit of power switch must exceed 900 mA to avoid false trigger during normal operation. For the TPS2065C device, target 1-A continuous output current application.
  3. What is the maximum allowable current provided by up-stream power, the maximum current limit of power switch that must lower it to ensure power switch can protect the up-stream power when overload is encountered at the output of power switch. For the TPS2065C device, the maximum IOS is 1.8 A.

9.2.2 Detailed Design Procedure

To begin the design process a few parameters must be decided upon. The designer must know the following:

  1. Normal input operation voltage
  2. Output continuous current
  3. Maximum up-stream power supply output current

9.2.2.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device; the actual capacitance must be optimized for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic bypass capacitor between IN and GND, as close to the device as possible for local noise decoupling.

All protection circuits such as the TPS20xxC and TPS20xxC-2 has the potential for input voltage overshoots and output voltage undershoots.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the abrupt reduction of output short-circuit current when the TPS20xxC and TPS20xxC-2 turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the TPS20xxC and TPS20xxC-2 output is shorted. Applications with large input inductance (for example, connecting the evaluation board to the bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current limit speed of the TPS20xxC and TPS20xxC-2 to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of 1 µF to 22 µF adjacent to the TPS20xxC and TPS20xxC-2 input aids in both speeding the response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted.

Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS20xxC and TPS20xxC-2 has abruptly reduced OUT current. Energy stored in the inductance drives the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB standard applications, a 120-µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of capacitance, and there is potential to drive the output negative, then TI recommends a minimum of 10-µF ceramic capacitance on the output. The voltage undershoot must be controlled to less than 1.5 V for 10 µs.

9.2.3 Application Curves

TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G001_2065_Rise_Fall_5Ohm.png
Figure 24. TPS2065C Output Rise / Fall 5 Ω
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G003_2065_EN_into_Shrt.png
Figure 26. TPS2065C Enable into Output Short
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G005_2065_Short_App.png
Figure 28. TPS2065C Short Applied
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G007_2065_Hot_Shrt.png
Figure 30. TPS2065C 50-mΩ Short Circuit
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G009_2065_Power_Down.png
Figure 32. TPS2065C Power Down – Enabled
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G011_2001_EN_into_Shrt.png
Figure 34. TPS2001C Enable into Short
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G013_2051_Turn_On.png
Figure 36. TPS2051C Turnon into 10 Ω
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G015_2051_Pulsed_Out_Shrt.png
Figure 38. TPS2051C Pulsed Output Short
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G017_2069_EN_into_Shrt.png
Figure 40. TPS2069C Enable into Short
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G002_2065_Rise_Fall_100Ohm.png
Figure 25. TPS2065C Output Rise / Fall 100 Ω
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G004_2065_Pulsed_Short_App.png
Figure 27. TPS2065C Pulsed Short Applied
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G006_2065_Pulsed.png
Figure 29. TPS2065C Pulsed 1.45-A Load
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G008_2065_Power_Up.png
Figure 31. TPS2065C Power Up – Enabled
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G010_2001_Turn_On.png
Figure 33. TPS2001C Turnon into 2.5 Ω
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G012_2001_Pulsed_Out_Shrt.png
Figure 35. TPS2001C Pulsed Output Short
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G014_2051_EN_into_Shrt.png
Figure 37. TPS2051C Enable into Short
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G016_2069_Turn_On.png
Figure 39. TPS2069C Turnon into 3.3 Ω
TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C TPS2069C TPS2069C-2 G018_2069_Pulsed_Out_Shrt.png
Figure 41. TPS2069C Pulsed Output Short