SLVSCT5D March   2015  – September 2016 TPS22953 , TPS22954

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics—VBIAS = 5 V
    7. 7.7  Electrical Characteristics—VBIAS = 3.3 V
    8. 7.8  Electrical Characteristics—VBIAS = 2.5 V
    9. 7.9  Switching Characteristics—CT = 1000 pF
    10. 7.10 Switching Characteristics—CT = 0 pF
    11. 7.11 Typical DC Characteristics
    12. 7.12 Typical Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  On and Off Control (EN pin)
      2. 9.3.2  Voltage Monitoring (SNS Pin)
      3. 9.3.3  Power Good (PG Pin)
      4. 9.3.4  Supervisor Fault Detection and Automatic Restart
      5. 9.3.5  Manual Restart
      6. 9.3.6  Thermal Shutdown
      7. 9.3.7  Reverse Current Blocking (TPS22953 Only)
      8. 9.3.8  Quick Output Discharge (QOD) (TPS22954 Only)
      9. 9.3.9  VIN and VBIAS Voltage Range
      10. 9.3.10 Adjustable Rise Time (CT pin)
      11. 9.3.11 Power Sequencing
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input to Output Voltage Drop
      2. 10.1.2 Thermal Considerations
      3. 10.1.3 Automatic Power Sequencing
      4. 10.1.4 Monitoring a Downstream Voltage
      5. 10.1.5 Monitoring the Input Voltage
      6. 10.1.6 Break-Before-Make Power MUX (TPS22953 Only)
      7. 10.1.7 Make-Before-Break Power MUX (TPS22953 Only)
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DQC/DSQ Package
10 Pin WSON
Top View
TPS22954 TPS22953 Pinout_TopView.gif
DQC/DSQ Package
10 Pin WSON
Bottom View
TPS22954 TPS22953 Pinout_BottomView.gif

Pin Functions

PIN(1) I/O DESCRIPTION
NO. NAME
1 IN I Switch input. Bypass this input with a ceramic capacitor to GND
2
3 BIAS I Bias pin and power supply to the device
4 EN I Active high switch enable/disable input. Also acts as the input UVLO pin. Use external resistor divider to adjust the UVLO level. Do not leave floating.
5 GND — Device ground
6 CT O VOUT slew rate control. Place ceramic cap from CT to GND to change the VOUT slew rate of the device and limit the inrush current. CT Capacitormust be rated to 25 V or higher
7 PG O Power good. This pin is open drain which will pull low when the voltage on EN and/or SNS is below their respective VIL level
8 SNS I Sense pin. Use external resistor divider to adjust the power good level. Do not leave floating
9 OUT O Switch output
10
— Thermal Pad — Exposed thermal pad. Tie to GND
(1) Pinout applies to all package versions.