SLVSC71B December   2013  – March 2020 TPS22966-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VBIAS = 5 V
    6. 6.6 Electrical Characteristics: VBIAS = 2.5 V
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1. 6.8.1 Typical AC Scope Captures at TA = 25ºC, CT = 1 nF
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Quick Output Discharge
      2. 8.3.2 ON/OFF Control
      3. 8.3.3 Adjustable Rise Time
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Capacitor (Optional)
      2. 9.1.2 Output Capacitor (Optional)
      3. 9.1.3 VIN and VBIAS Voltage Range
      4. 9.1.4 Safe Operating Area (SOA)
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Adjustable Rise Time

A capacitor to GND on the CTx pins sets the slew rate for each channel. To ensure desired performance, a capacitor with a minimum voltage rating of 25 V should be used on the CTx pin. An approximate formula for the relationship between CTx and slew rate is (the equation below accounts for 10% to 90% measurement on VOUT and does NOT apply for CTx = 0 pF. Use Table 1 to determine rise times for when CTx = 0 pF):

Equation 1. TPS22966-Q1 eq1_lvsbh4.gif

where

  • SR = slew rate (in µs/V)
  • CT = the capacitance value on the CTx pin (in pF)
  • The units for the constant 13.7 is in µs/V.

Rise time can be calculated by multiplying the input voltage by the slew rate. Table 1 shows rise time values measured on a typical device. Rise times shown below are only valid for the power-up sequence where VIN and VBIAS are already in steady state condition, and the ON pin is asserted high.

Table 1. Rise Time Values

CTx (pF) RISE TIME (µs) 10% - 90%, CL = 0.1µF, CIN = 1µF, RL = 10Ω
TYPICAL VALUES at 25°C, VBIAS = 5V, 25V X7R 10% CERAMIC CAP
5V 3.3V 1.8V 1.5V 1.2V 1.05V 0.8V
0 124 88 63 60 53 49 42
220 481 323 193 166 143 133 109
470 855 603 348 299 251 228 175
1000 1724 1185 670 570 469 411 342
2200 3328 2240 1308 1088 893 808 650
4700 7459 4950 2820 2429 1920 1748 1411
10000 16059 10835 6040 5055 4230 3770 3033