SLVSER7 October   2020 TPS23731

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: DC-DC Controller Section
    6. 7.6 Electrical Characteristics PoE
    7.     14
    8. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLS Classification
      2. 8.3.2  DEN Detection and Enable
      3. 8.3.3  APD Auxiliary Power Detect
      4. 8.3.4  Internal Pass MOSFET
      5. 8.3.5  T2P and APDO Indicators
      6. 8.3.6  DC-DC Controller Features
        1. 8.3.6.1 VCC, VB, VBG and Advanced PWM Startup
        2.       27
        3. 8.3.6.2 CS, Current Slope Compensation and blanking
        4. 8.3.6.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
        5. 8.3.6.4 FRS Frequency Setting and Synchronization
        6. 8.3.6.5 DTHR and Frequency Dithering for Spread Spectrum Applications
        7. 8.3.6.6 SST and Soft-Start of the Switcher
        8. 8.3.6.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
      7. 8.3.7  Switching FET Driver - GATE
      8. 8.3.8  EMPS and Automatic MPS
      9. 8.3.9  VDD Supply Voltage
      10. 8.3.10 RTN, AGND, GND
      11. 8.3.11 VSS
      12. 8.3.12 Exposed Thermal pads - PAD_G and PAD_S
    4. 8.4 Device Functional Modes
      1. 8.4.1  PoE Overview
      2. 8.4.2  Threshold Voltages
      3. 8.4.3  PoE Start-Up Sequence
      4. 8.4.4  Detection
      5. 8.4.5  Hardware Classification
      6. 8.4.6  Maintain Power Signature (MPS)
      7. 8.4.7  Advanced Start-Up and Converter Operation
      8. 8.4.8  Line Undervoltage Protection and Converter Operation
      9. 8.4.9  PD Self-Protection
      10. 8.4.10 Thermal Shutdown - DC-DC Controller
      11. 8.4.11 Adapter ORing
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Input Bridges and Schottky Diodes
          2. 9.2.1.1.2  Input TVS Protection
          3. 9.2.1.1.3  Input Bypass Capacitor
          4. 9.2.1.1.4  Detection Resistor, RDEN
          5. 9.2.1.1.5  Classification Resistor, RCLS.
          6. 9.2.1.1.6  APD Pin Divider Network, RAPD1, RAPD2
          7. 9.2.1.1.7  Setting Frequency (RFRS) and Synchronization
          8. 9.2.1.1.8  Bias Supply Requirements and CVCC
          9. 9.2.1.1.9  APDO, T2P Interface
          10. 9.2.1.1.10 Output Voltage Feedback Divider, RAUX, R1,R2
          11. 9.2.1.1.11 Frequency Dithering for Conducted Emissions Control
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 EMI Containment
    4. 11.4 Thermal Considerations and OTSD
    5. 11.5 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

PoE Overview

The following text is intended as an aid in understanding the operation of the TPS23731, but it is not a substitute for the actual IEEE 802.3bt or 802.3at standards. The IEEE 802.3bt standard is an update to IEEE 802.3-2018, adding Clause 145 (PoE), including power delivery using all four pairs, high-power options, additional features to reduce standby power consumption and enhanced classification.

Generally speaking, a device compliant to IEEE 802.3-2012 is referred to as a Type 1 (Class 0-3) or 2 (Class 4) device, and devices with higher power and enhanced classification is referred to as Type 3 (Class 5, 6) or 4 (Class 7, 8) devices. Type 3 devices will also include Class 0-4 devices that are 4-pair capable. Standards change and must always be referenced when making design decisions.

The IEEE 802.3at and 802.3bt standards define a method of safely powering a PD (powered device) over a cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. There is also a fourth operational state used by Type 3 and 4 PSEs, called "connection check", to determine if the PD has same (single interface) or independent (dual interface or commonly referred to "dual-signature" in the IEEE802.3bt standard) classification signature on each pairset. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as detection. The low power levels used during detection and connection check are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as classification. The PSE may then power the PD if it has adequate capacity.

Type 3 or Type 4 PSEs are required to do an enhanced hardware classification of Type 3 or 4 respectively. Type 2 PSEs are required to do Type 1 hardware classification plus a data-layer classification, or an enhanced Type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A Type 3 or Type 4 PD must do respectively Type 3 or Type 4 hardware classification as well as DLL classification. A Type 2 PD must do Type 2 hardware classification as well as DLL classification. The PD may return the default, 13-W current-encoded class, or one of four other choices if Type 2, one of six other choices if Type 3, and one of eight other choices if Type 4. DLL classification occurs after power-on and the Ethernet data link has been established

Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 8-5 shows the operational states as a function of PD input voltage.

GUID-04411240-4118-4F4E-AEEA-19337734C847-low.gifFigure 8-5 Operational States

The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops and operating margin. The standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation. IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA-568) that may have had AWG 26 conductors. IEEE 802.3at Type 2 and IEEE 802.3bt Type 3 cabling power loss allotments and voltage drops have been adjusted for 12.5-Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568, typically AWG 24 conductors). Table 8-3 shows key operational limits broken out for the two revisions of the standard.

Table 8-3 Comparison of Operational Limits
STANDARDPOWER LOOP
RESISTANCE (MAX)
PSE OUTPUT
POWER (MIN)
PSE STATIC OUTPUT
VOLTAGE (MIN)
PD INPUT
POWER (MAX)
STATIC PD INPUT VOLTAGE
POWER ≤ 13 WPOWER > 13 W
IEEE802.3-2012
802.3at (Type 1)
20 Ω15.4 W44 V13 W37 V – 57 VN/A
802.3bt (Type 3)12.5 Ω50 V
802.3at (Type 2)
802.3bt (Type 3)
12.5 Ω30 W50 V25.5 W37 V – 57 V42.5 V – 57 V
802.3bt (Type 3)6.25 Ω (4-pair)60 W50 V51 WN/A42.5 V - 57 V
802.3bt (Type 4)6.25 Ω (4-pair)90 W52 V71.3 WN/A41.2 V - 57 V

The PSE can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between the two spare pairs (4–5 and 7–8). Power application to the same pin combinations in 1000/2.5G/5G/10GbaseT systems is recognized in IEEE 802.3bt. 1000/2.5G/5G/10GbaseT systems can handle data on all pairs, eliminating the spare pair terminology. Type 1 and 2 PSEs are allowed to apply voltage to only one set of pairs at a time, while Type 3 and 4 PSEs may apply power to one or both sets of pairs at a time. The PD uses input diode or active bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS23731 specifications.

A compliant Type 2, 3 or 4 PD has power management requirements not present with a Type 1 PD. These requirements include the following:

  1. Must interpret respectively Type 2, 3 or 4 hardware classification.
  2. Must present hardware Class 4 during the first two classfication events, applicable to Type 2 and 4 PDs, as well as to Type 3 PD with Class level 4 or higher.
  3. If Type 3 Class 5-6 or Type 4 single interface PD, it must present hardware Class in the range of 0 to 3 during the third and any subsequent classification events.
  4. Must implement DLL negotiation.
  5. Must draw less than 400 mA from 50 ms until 80 ms after the PSE applies operation voltage (power up), if Type 2 or 3, single interface PD. This covers the PSE inrush period, which is 75 ms maximum.
  6. Must draw less than 800 mA total and 600 mA per pairset from 50 ms until 80 ms after the PSE applies operation voltage (power up), if Type 4 (Class 7-8) single interface PD.
  7. Must not draw more than 60 mA and 5 mA any time the input voltage falls below respectively 30 V and 10 V.
  8. Must not draw more than 13 W if it has not received at least a Type 2 hardware classification or received permission through DLL.
  9. Must not draw more than 25.5 W if it has not received at least 4 classification events or received permission through DLL.
  10. Must not draw more than 51 W if it has not received at least 5 classification events or received permission through DLL.
  11. Must meet various operating and transient templates.
  12. Optionally monitor for the presence or absence of an adapter.

As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for changes. APDO can also be used in cases where the design needs to know specifically if an adapter is plugged in and operational.