SLVSCA1B Data sheet

SLVSCA1B October 2013 – August 2016 TPS2546-Q1

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RTE|16
- MPQF149D

Thermal pad, mechanical data (Package|Pins)

RTE|16
- QFND525B

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	IN, EN, ILIM_LO, ILIM_HI, FAULT, STATUS, ILIM_SEL, CTL1, CTL2, CTL3, OUT	–0.3	7	V
	IN to OUT	–7	7
	DP_IN, DM_IN, DP_OUT, DM_OUT	–0.3	(IN + 0.3) or 5.7
Input clamp current	DP_IN, DM_IN, DP_OUT, DM_OUT		±20	mA
Continuous current in SDP or CDP mode	DP_IN to DP_OUT or DM_IN to DM_OUT		±100	mA
Continuous current in BC1.2 DCP mode	DP_IN to DM_IN		±50	mA
Continuous output current	OUT	Internally limited
Continuous output sink current	FAULT, STATUS		25	mA
Continuous output source current	ILIM_LO, ILIM_HI	Internally limited		mA
Operating junction temperature, T_J		–40	Internally limited	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±2000⁽²⁾	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011		±750⁽³⁾	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) The passing level per AEC-Q100 Classification H2.

(3) The passing level per AEC-Q100 Classification C5.

6.3 Recommended Operating Conditions

voltages are referenced to GND (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input voltage, IN	4.5	5.5	V
	Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL	0	5.5	V
	Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT	0	V_IN	V
V_IH	High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL	1.8		V
V_IL	Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL		0.8	V
	Continuous current, data line inputs, SDP or CDP mode, DP_IN to DP_OUT, DM_IN to DM_OUT		±30	mA
	Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to DM_IN		±15	mA
I_OUT	Continuous output current, OUT	0	2.5	A
	Continuous output sink current, FAULT, STATUS	0	10	mA
R_{ILIM_XX}	Current-limit set resistors	16.9	750	kΩ
T_J	Operating virtual junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS2546-Q1	UNIT
		RTE (WQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	53.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	51.4	°C/W
R_θJB	Junction-to-board thermal resistance	17.2	°C/W
ψ_JT	Junction-to-top characterization parameter	3.7	°C/W
ψ_JB	Junction-to-board characterization parameter	20.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Unless otherwise noted: –40 ≤ T_J ≤ 125°C, 4.5 V ≤ V_IN ≤ 5.5 V, V_EN = V_IN, V_{ILIM_SEL} = V_IN, V_CTL1 = V_CTL2 = V_CTL3 = V_IN. R_FAULT = R_STATUS = 10 kΩ, R_{ILIM_HI} = 20 kΩ, R_{ILIM_LO} = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SWITCH
R_DS(on)	ON resistance⁽¹⁾	T_J = 25°C, I_OUT = 2 A		73	84	mΩ
		–40°C ≤ T_J ≤ 85°C, I_OUT = 2 A		73	105
		–40°C ≤ T_J ≤ 125°C, I_OUT = 2 A		73	120
t_r	OUT voltage rise time	V_IN = 5 V, C_L = 1 µF, R_L = 100 Ω (see Figure 23 and Figure 24)	0.7	1	1.6	ms
t_f	OUT voltage fall time		0.2	0.35	0.5	ms
t_on	OUT voltage turnon time	V_IN = 5 V, C_L = 1 µF, R_L = 100 Ω (see Figure 23 and Figure 25)		2.7	4	ms
t_off	OUT voltage turnoff time			1.7	3	ms
I_REV	Reverse leakage current	V_OUT = 5.5 V, V_IN = V_EN = 0 V, –40 ≤ T_J ≤ 85°C, Measure I_OUT			2	µA
DISCHARGE
R_DCHG	OUT discharge resistance		400	500	630	Ω
t_{DCHG_L}	Long OUT discharge hold time	Time V_OUT < 0.7 V (see Figure 26)	1.3	2	2.9	s
t_{DCHG_S}	Short OUT discharge hold time	Time V_OUT < 0.7 V (see Figure 26)	205	310	450	ms
EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS
	Input pin rising logic threshold voltage		1	1.35	1.7	V
	Input pin falling logic threshold voltage		0.85	1.15	1.45
	Hysteresis⁽²⁾			200		mV
	Input current	Pin voltage = 0 V or 5.5 V	–0.5		0.5	µA
ILIMSEL CURRENT LIMIT
I_OS	OUT short-circuit current limit⁽¹⁾	V_{ILIM_SEL} = 0 V, R_{ILIM_LO} = 210 kΩ	205	240	275	mA
		V_{ILIM_SEL} = 0 V, R_{ILIM_LO} = 80.6 kΩ	575	625	680
		V_{ILIM_SEL} = 0 V, R_{ILIM_LO} = 22.1 kΩ	2120	2275	2430
		V_{ILIM_SEL} = V_IN, R_{ILIM_HI}= 20 kΩ	2340	2510	2685
		V_{ILIM_SEL} = V_IN, R_{ILIM_HI} = 16.9 kΩ	2770	2970	3170
t_IOS	Response time to OUT short-circuit⁽²⁾	V_IN = 5 V, R = 0.1Ω, lead length = 2 inches (see Figure 27)		1.5		µs
SUPPLY CURRENT
I_{IN_OFF}	Disabled IN supply current	V_EN = 0 V, V_OUT = 0 V, –40 ≤ T_J ≤ 85°C		0.1	2	µA
I_{IN_ON}	Enabled IN supply current	V_CTL1 = V_CTL2 = V_IN, V_CTL3 = 0 V, V_{ILIM_SEL} = 0 V		165	220	µA
		V_CTL1 = V_CTL2 = V_CTL3 = V_IN, V_{ILIM_SEL} = 0 V		175	230
		V_CTL1 = V_CTL2 = V_IN, V_CTL3 = 0 V, V_{ILIM_SEL} = V_IN		185	240
		V_CTL1 = V_CTL2 = V_IN, V_CTL3 = VIN, V_{ILIM_SEL} = V_IN		195	250
		V_CTL1 = 0 V, V_CTL2 = V_CTL3 = V_IN		215	270
UNDERVOLTAGE LOCKOUT
V_UVLO	IN rising UVLO threshold voltage		3.9	4.1	4.3	V
	Hysteresis⁽²⁾			100		mV
FAULT
	Output low voltage	I_FAULT = 1 mA			100	mV
	OFF-state leakage	V_FAULT = 5.5 V			1	µA
	Overcurrent FAULT rising and falling deglitch		5	8.2	12	ms
STATUS
	Output low voltage	I_STATUS = 1 mA			100	mV
	OFF-state leakage	V_STATUS = 5.5 V			1	µA
THERMAL SHUTDOWN
	Thermal shutdown threshold		155			°C
	Thermal shutdown threshold in current-limit		135
	Hysteresis⁽²⁾			20

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account separately.

(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

6.6 Electrical Characteristics: High-Bandwidth Switch

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
HIGH-BANDWIDTH ANALOG SWITCH
	DP/DM switch ON resistance	V_{DP/DM_OUT} = 0 V, I_{DP/DM_IN} = 30 mA	2	4	Ω
	DP/DM switch ON resistance	V_{DP/DM_OUT} = 2.4 V, I_{DP/DM_IN} = –15 mA	3	6	Ω
	Switch resistance mismatch between DP / DM channels	V_{DP/DM_OUT} = 0 V, I_{DP/DM_IN} = 30 mA	0.05	0.15	Ω
	Switch resistance mismatch between DP / DM channels	V_{DP/DM_OUT} = 2.4 V, I_{DP/DM_IN} = –15 mA	0.05	0.15	Ω
	DP/DM switch OFF-state capacitance⁽¹⁾	V_EN= 0 V, V_{DP/DM_IN} = 0.3 V, V_ac = 0.6 V_pk–pk, f = 1 MHz	3		pF
	DP/DM switch ON-state capacitance⁽²⁾	V_{DP/DM_IN} = 0.3 V, V_ac = 0.6 V_pk-pk, f = 1 MHz	5.4		pF
O_IRR	OFF-state isolation⁽³⁾	V_EN= 0 V, f = 250 MHz	33		dB
X_TALK	ON-state cross channel isolation⁽³⁾	f = 250 MHz	52		dB
	OFF-state leakage current	V_EN = 0 V, V_{DP/DM_IN} = 3.6 V, V_{DP/DM_OUT} = 0 V, measure I_{DP/DM_OUT}	0.1	1.5	µA
BW	Bandwidth (–3 dB)⁽³⁾	R_L = 50 Ω	2.6		GHz
t_pd	Propagation delay⁽³⁾		0.25		ns
t_SK	Skew between opposite transitions of the same port (t_PHL – t_PLH)		0.1		ns

(1) The resistance in series with the parasitic capacitance to GND is typically 250 Ω.

(2) The resistance in series with the parasitic capacitance to GND is typically 150 Ω

(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

6.7 Electrical Characteristics: Charging Controller

Unless otherwise noted: –40 ≤ T_J ≤ 125°C, 4.5 V ≤ V_IN ≤ 5.5 V, V_EN = V_IN, V_{ILIM_SEL} = V_IN, V_CTL1 = 0 V, V_CTL2 = V_CTL3 = V_IN. R_FAULT = R_STATUS = 10 kΩ, R_{ILIM_HI} = 20 kΩ, R_{ILIM_LO} = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SHORTED MODE (BC1.2 DCP)
	DP_IN / DM_IN shorting resistance	VCTL1 = VIN, VCTL2 = VCTL3 = 0 V			125	200	Ω
1.2 V MODE
	DP_IN /DM_IN output voltage	VCTL1 = VIN, VCTL2 = VCTL3 = 0 V		1.19	1.25	1.31	V
	DP_IN /DM_IN output impedance	VCTL1 = VIN, VCTL2 = VCTL3 = 0 V		60	75	94	kΩ
DIVIDER1 MODE
	DP_IN divider1 output voltage	VCTL1 = VIN, VCTL2 = VCTL3 = 0 V		1.9	2	2.1	V
	DM_IN divider1 output voltage			2.57	2.7	2.84	V
	DP_IN output impedance			8	10.5	12.5	kΩ
	DM_IN output impedance			8	10.5	12.5	kΩ
DIVIDER2 MODE
	DP_IN divider2 output voltage	IOUT = 1 A		2.57	2.7	2.84	V
	DM_IN divider2 output voltage			1.9	2	2.1	V
	DP_IN output impedance			8	10.5	12.5	kΩ
	DM_IN output impedance			8	10.5	12.5	kΩ
CHARGING DOWNSTREAM PORT
V_{DM_SRC}	DM_IN CDP output voltage	VCTL1 = VCTL2 = VCTL3 = VIN	V_{DP_IN} = 0.6 V, –250 µA < I_{DM_IN} < 0 µA	0.5	0.6	0.7	V
V_{DAT_REF}	DP_IN rising lower window threshold for V_{DM_SRC} activation	VCTL1 = VCTL2 = VCTL3 = VIN		0.25		0.4	V
	Hysteresis⁽¹⁾				50		mV
V_{LGC_SRC}	DP_IN rising upper window threshold for V_{DM_SRC} de-activation			0.8		1	V
	Hysteresis⁽¹⁾				100		mV
I_{DP_SINK}	DP_IN sink current	VCTL1 = VCTL2 = VCTL3 = VIN	V_{DP_IN} = 0.6 V	40	70	100	µA
LOAD DETECT – NON-POWER WAKE
I_LD	IOUT rising load detect current threshold	VCTL1 = VCTL2 = VCTL3 = VIN		635	700	765	mA
	Hysteresis⁽¹⁾				50		mA
t_{LD_SET}	Load detect set time			140	200	275	ms
	Load detect reset time			1.9	3	4.2	s
LOAD DETECT – POWER WAKE
I_{OS_PW}	Power wake short-circuit current limit	VCTL1 = VCTL2 = 0 V, VCTL3 = VIN		32	55	78	mA
	I_OUT falling power wake reset current detection threshold			23	45	67	mA
	Reset current hysteresis⁽¹⁾				5		mA
	Power wake reset time			10.7	15	20.6	s

(1) These parameters are provided for reference only and do not constitute part of Texas Instrument's published device specifications for purposes of Texas Instrument's product warranty.