SLVSCV0B August 2015 – September 2016
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPA25923x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in controlling the in-rush current and provides precise current limiting during overload conditions for systems such as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device. Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web folder. This section presents a simplified discussion of the design process.
Table 2 shows the design parameters for this application.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage range, V_{IN} | 5 V |
Undervoltage lockout set point, V_{(UV)} | Default: V_{UVR} = 4.3 V |
Overvoltage protection set point, V_{(OV)} | Default: V_{OVC} = 6.1 V |
Load at start-up, R_{L(SU)} | 2 Ω |
Current limit, I_{OL} = I_{ILIM} | 3.7 A |
Load capacitance, C_{OUT} | 1 µF |
Maximum ambient temperature, T_{A} | 85°C |
The following design procedure can be used to select component values for the TPS25923x.
This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.
The R_{ILIM} resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4:
For I_{OL} = I_{ILIM} = 3.7 A, from Equation 4, R_{ILIM} = 100 kΩ. Choose closest standard value resistor with 1% tolerance.
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R_{1} and R_{2} as connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage are calculated solving Equation 5:
Where V_{ENR} = 1.4 V, is enable voltage rising threshold.
Since R_{1} and R_{2} leak the current from input supply (VIN), these resistors must be selected based on the acceptable leakage current from input power supply (VIN). The current drawn by R_{1} and R_{2} from the power supply \{I_{R12} = V_{IN}/(R_{1} + R_{2})\}.
However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I_{R12} must be chosen to be 20x greater than the leakage current expected.
For default UVLO of V_{UVR} = 4.3 V, select R_{2} = OPEN, and R_{1} = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it cannot be connected directly to V_{IN} > 7 V. It has to be connected through R_{1} = 1 MΩ only, so that the pull-up current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, V_{UVR}. This is calculated using Equation 6:
Where V_{UVR} is 4.3V, Power fail threshold set is : V_{(PFAIL)} = 4.1 V.
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C_{dVdT} needed is calculated considering the two possible cases:
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across the internal FET decreases. The average power dissipated in the device during start-up is calculated using Equation 8.
For TPS25923x, the inrush current is determined using Equation 7:
Power dissipation during start-up is given by Equation 8:
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.
When load draws current during the turnon sequence, there is additional power dissipated. Considering a resistive load during start-up (R_{L(SU)}), load current ramps up proportionally with increase in output voltage during T_{dVdT} time. The average power dissipation in the internal FET during charging time due to resistive load is given by Equation 9:
Total power dissipated in the device during startup is given by Equation 10:
Total current during startup is given by Equation 11:
If I_{(STARTUP)} > I_{OL}, the device limits the current to I_{OL} and the current limited charging time is determined by Equation 12:
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as shown in Figure 40.
For the design example under discussion, select ramp-up capacitor C_{dVdT} = OPEN. Then, using Equation 2, we get Equation 13:
The inrush current drawn by the load capacitance (C_{OUT}) during ramp-up using Equation 7 is given by Equation 14:
The inrush Power dissipation is calculated, using Equation 8 as shown in Equation 15:
For 36 mW of power loss, the thermal shut down time of the device must not be less than the ramp-up time T_{dVdT} to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 40 at T_{A} = 85°C, for 36 mW of power, the shutdown time is infinite. So it is safe to use 350 µs as start-up time without any load on output.
Considering the start-up with load 2 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 9 is given by Equation 16:
The total device power dissipation during start up, using Equation 10 is:
From thermal shutdown limit graph at T_{A} = 85°C, the thermal shutdown time for 2.44 W is more than 100 ms. So it is well within acceptable limits to use no external capacitor (C_{dV/dT}) with start-up load of 2 Ω.
If, due to large C_{OUT}, there is a need to decrease the power loss during start-up, it can be done with increase of C_{dVdT }capacitor.
C_{VIN} is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C_{VIN}.
The design parameters for this design example are shown in Table 3.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage range, V_{IN} | 5 V |
Undervoltage lockout set point, V_{(UV)} | 4.5 V |
Overvoltage protection set point, V_{(OV)} | Default: V_{OVC} = 6.1 V |
Load at start-up, R_{L(SU)} | 1000 Ω |
Current limit, I_{OL}= I_{ILIM} | 3 A |
Load capacitance, C_{OUT} | 4700 µF |
Maximum ambient temperature, T_{A} | 85°C |
The R_{ILIM} resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
For I_{OL}= I_{ILIM} = 3 A, from Equation 4, R_{ILIM} = 76.8 kΩ, choose closest standard value resistor with 1% tolerance.
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R_{1} and R_{2} as connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage are calculated solving Equation 5.
For UVLO of V_{(UV)} = 4.5 V, select R_{2} = 453 kΩ, and R_{1} = 1 MΩ.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, V_{(UV)}. This is calculated using Equation 6.
Where V_{(UV)} = 4.5 V, Power fail threshold set is V_{(PFAIL)} = 4.33 V.
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
For the design example under discussion, select ramp-up capacitor C_{dVdT} = 22 nF. Then, using Equation 2 we get Equation 18:
The inrush current drawn by the load capacitance (C_{OUT}) during ramp-up using Equation 7 is given by Equation 19:
The inrush Power dissipation is calculated, using Equation 8 is given by Equation 20:
Considering the start-up with load 1000 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 9 is given by Equation 21:
The total device power dissipation during start up is:
From thermal shutdown limit graph at T_{A} = 85°C, the thermal shutdown time for 537 mW is more than 300 ms. So the device starts safely.
C_{VIN} is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C_{VIN}.
When the device is disabled, the output voltage is left floating and power down profile is entirely dictated by the load. In some applications, this can lead to undesired activity as the load is not powered down to a defined state. Controlled output discharge can ensure the load is turned off completely and not in an undefined operational state. The BFET pin in TPS25923x family of eFuses facilitates Quick Output Discharge (QOD) function as illustrated in Figure 46. When the device is/gets disabled, the BFET pin pulls low which enables the external P-MOSFET Q_{1} for discharge feature to function. The output voltage discharge rate is dictated by the output capacitor C_{OUT}, the discharge resistance R_{DCHG} and the load.