SLVSCV0B August   2015  – September 2016

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 GND
      2. 8.3.2 VIN
      3. 8.3.3 dV/dT
      4. 8.3.4 BFET
      5. 8.3.5 EN/UVLO
      6. 8.3.6 ILIM
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step by Step Design Procedure
          2. 9.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
          3. 9.2.1.2.3 Undervoltage Lockout Set Point
          4. 9.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
            1. 9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
            2. 9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
          5. 9.2.1.2.5 Support Component Selection—CVIN
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection
          2. 9.2.2.2.2 Undervoltage Lockout Set Point
          3. 9.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT)
          4. 9.2.2.2.4 Support Component Selection - CVIN
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Controlled Power Down using TPS25923x
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPA25923x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in controlling the in-rush current and provides precise current limiting during overload conditions for systems such as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust protection for multiple faults on the sub-system rail.

The following design procedure can be used to select component values for the device. Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web folder. This section presents a simplified discussion of the design process.

9.2 Typical Applications

9.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes

TPS259230 TPS259231 App_Diag2_slvscv0.gif Figure 39. Typical Application Schematic: Simple 3.7-A eFuse for STBs

9.2.1.1 Design Requirements

Table 2 shows the design parameters for this application.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range, VIN 5 V
Undervoltage lockout set point, V(UV) Default: VUVR = 4.3 V
Overvoltage protection set point, V(OV) Default: VOVC = 6.1 V
Load at start-up, RL(SU) 2 Ω
Current limit, IOL = IILIM 3.7 A
Load capacitance, COUT 1 µF
Maximum ambient temperature, TA 85°C

9.2.1.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS25923x.

9.2.1.2.1 Step by Step Design Procedure

This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.

9.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection

The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4:

Equation 4. TPS259230 TPS259231 eq4_lvscq3.gif

For IOL = IILIM = 3.7 A, from Equation 4, RILIM = 100 kΩ. Choose closest standard value resistor with 1% tolerance.

9.2.1.2.3 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage are calculated solving Equation 5:

Equation 5. TPS259230 TPS259231 eq5_slvscq3.gif

Where VENR = 1.4 V, is enable voltage rising threshold.

Since R1 and R2 leak the current from input supply (VIN), these resistors must be selected based on the acceptable leakage current from input power supply (VIN). The current drawn by R1 and R2 from the power supply \{IR12 = VIN/(R1 + R2)\}.

However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, IR12 must be chosen to be 20x greater than the leakage current expected.

For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it cannot be connected directly to VIN > 7 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up current for EN/UVLO pin is limited to < 20 µA.

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, VUVR. This is calculated using Equation 6:

Equation 6. V(PFAIL) = 0.96 x VUVR

Where VUVR is 4.3V, Power fail threshold set is : V(PFAIL) = 4.1 V.

9.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)

For a successful design, the junction temperature of device must be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

The ramp-up capacitor CdVdT needed is calculated considering the two possible cases:

9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up

During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across the internal FET decreases. The average power dissipated in the device during start-up is calculated using Equation 8.

For TPS25923x, the inrush current is determined using Equation 7:

Equation 7. TPS259230 TPS259231 eq7_lvscq3.gif

Power dissipation during start-up is given by Equation 8:

Equation 8. TPS259230 TPS259231 eq_15_slvsce9.gif

Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.

9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up

When load draws current during the turnon sequence, there is additional power dissipated. Considering a resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during TdVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given by Equation 9:

Equation 9. TPS259230 TPS259231 eq_19_slvsce9.gif

Total power dissipated in the device during startup is given by Equation 10:

Equation 10. TPS259230 TPS259231 eq_20_slvsce9.gif

Total current during startup is given by Equation 11:

Equation 11. TPS259230 TPS259231 eq_21_slvsce9.gif

If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by Equation 12:

Equation 12. TPS259230 TPS259231 eq12_slvscq3.gif

The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as shown in Figure 40.

TPS259230 TPS259231 D039_SLVSCV0.gif Figure 40. Thermal Shutdown Limit Plot

For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2, we get Equation 13:

Equation 13. TPS259230 TPS259231 eq13_lvscu2.gif

The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7 is given by Equation 14:

Equation 14. TPS259230 TPS259231 eq14_lvscu2.gif

The inrush Power dissipation is calculated, using Equation 8 as shown in Equation 15:

Equation 15. TPS259230 TPS259231 eq15_lvscu2.gif

For 36 mW of power loss, the thermal shut down time of the device must not be less than the ramp-up time TdVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 40 at TA = 85°C, for 36 mW of power, the shutdown time is infinite. So it is safe to use 350 µs as start-up time without any load on output.

Considering the start-up with load 2 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 9 is given by Equation 16:

Equation 16. TPS259230 TPS259231 eq16_lvscu2.gif

The total device power dissipation during start up, using Equation 10 is:

Equation 17. TPS259230 TPS259231 eq17_lvscu2.gif

From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 2.44 W is more than 100 ms. So it is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 2 Ω.

If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of CdVdT capacitor.

9.2.1.2.5 Support Component Selection—CVIN

CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.

9.2.1.3 Application Curves

TPS259230 TPS259231 sec9_2_1_4_plot1_lvscu2.png
Figure 41. Output Ramp without Load on Output
TPS259230 TPS259231 sec9_2_1_4_plot2_lvscu2.png
Figure 42. Output Ramp with 2-Ω Load at Start Up

9.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)

TPS259230 TPS259231 Inrush_slvscv0.gif Figure 43. Inrush and Reverse Current Protection for Hold-Up Capacitor Application (For Example, SSD)
(TPS25923x UVLO is Used as Power Fail Comparator)

9.2.2.1 Design Requirements

The design parameters for this design example are shown in Table 3.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range, VIN 5 V
Undervoltage lockout set point, V(UV) 4.5 V
Overvoltage protection set point, V(OV) Default: VOVC = 6.1 V
Load at start-up, RL(SU) 1000 Ω
Current limit, IOL= IILIM 3 A
Load capacitance, COUT 4700 µF
Maximum ambient temperature, TA 85°C

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection

The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.

For IOL= IILIM = 3 A, from Equation 4, RILIM = 76.8 kΩ, choose closest standard value resistor with 1% tolerance.

9.2.2.2.2 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage are calculated solving Equation 5.

For UVLO of V(UV) = 4.5 V, select R2 = 453 kΩ, and R1 = 1 MΩ.

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, V(UV). This is calculated using Equation 6.

Where V(UV) = 4.5 V, Power fail threshold set is V(PFAIL) = 4.33 V.

9.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT)

For a successful design, the junction temperature of device must be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

For the design example under discussion, select ramp-up capacitor CdVdT = 22 nF. Then, using Equation 2 we get Equation 18:

Equation 18. TPS259230 TPS259231 eq18_lvscu2.gif

The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7 is given by Equation 19:

Equation 19. TPS259230 TPS259231 eq19_lvscu2.gif

The inrush Power dissipation is calculated, using Equation 8 is given by Equation 20:

Equation 20. TPS259230 TPS259231 eq20_lvscu2.gif

Considering the start-up with load 1000 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 9 is given by Equation 21:

Equation 21. TPS259230 TPS259231 eq21_lvscu2.gif

The total device power dissipation during start up is:

Equation 22. TPS259230 TPS259231 eq22_lvscu2.gif

From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 537 mW is more than 300 ms. So the device starts safely.

9.2.2.2.4 Support Component Selection - CVIN

CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.

9.2.2.3 Application Curves

TPS259230 TPS259231 Sec10_2_2_4_Fig1_lvscu2.png
COUT = CHOLD-UP = 4700 µF CdVdT = 22 nF
Figure 44. Output Ramp Up
TPS259230 TPS259231 Sec10_2_2_4_Fig2_lvscu2.png
COUT = CHOLD-UP = 4700 µF V(PFAIL) = 4.33 V RLOAD = 5 Ω
Figure 45. Hold-Up Power when VIN fails

9.2.3 Controlled Power Down using TPS25923x

When the device is disabled, the output voltage is left floating and power down profile is entirely dictated by the load. In some applications, this can lead to undesired activity as the load is not powered down to a defined state. Controlled output discharge can ensure the load is turned off completely and not in an undefined operational state. The BFET pin in TPS25923x family of eFuses facilitates Quick Output Discharge (QOD) function as illustrated in Figure 46. When the device is/gets disabled, the BFET pin pulls low which enables the external P-MOSFET Q1 for discharge feature to function. The output voltage discharge rate is dictated by the output capacitor COUT, the discharge resistance RDCHG and the load.

TPS259230 TPS259231 Quick_Output_Discharge_TPS25923.gif Figure 46. . Circuit Implementation with Quick Output Discharge Function