SLVSDT4F October   2017  – December 2021 TPS2662

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout (UVLO)
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Hot Plug-In and Inrush Current Control
      4. 9.3.4 Reverse Polarity Protection
        1. 9.3.4.1 Input Side Reverse Polarity Protection
        2. 9.3.4.2 Output Side Reverse Polarity Protection
      5. 9.3.5 Overload and Short-Circuit Protection
        1. 9.3.5.1 Overload Protection
        2.       28
        3. 9.3.5.2 Short-Circuit Protection
          1. 9.3.5.2.1 Start-Up With Short-Circuit On Output
      6. 9.3.6 Reverse Current Protection
      7. 9.3.7 FAULT Response
      8. 9.3.8 IN, OUT, RTN, and GND Pins
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low Current Shutdown Control (SHDN)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step-by-Step Design Procedure
        2. 10.2.2.2 Programming the Current Limit Threshold R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Setting Output Voltage Ramp Time—(tdVdT)
          1. 10.2.2.4.1 Case 1: Start-Up Without Load—Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.4.2 Case 2: Start-Up With Load —Output Capacitance C(OUT) and Load Draws Current During Start-Up
          3. 10.2.2.4.3 Support Component Selections – R FLT and C(IN)
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Field Supply Protection in PLC, DCS I/O Modules
      2. 10.3.2 Simple 24-V Power Supply Path Protection
      3. 10.3.3 Power Stealing in Smart Thermostat
    4. 10.4 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
IN and UVLO INPUT
UVLO_tON(dly)UVLO Turnon DelayUVLO ↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dVdT) = Open51µs
UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dVdT) > 4.7 nF,  [C(dVdT) in nF]51 + 27.4 x C(dVdT)µs
UVLO_toff(dly)UVLO Turnoff delayUVLO↓ (100 mV below V(UVLOF)) to FLT↓6.14µs
SHUTDOWN CONTROL INPUT ( SHDN)
tSD(dly)SHUTDOWN exit delaySHDN↑ to V(OUT) = 100 mV, C(dVdT) = Open156µs
SHDN↑ to V(OUT) = 100 mV, C(dVdT) > 4.7 nF, [C(dVdT) in nF]156 + 27.4 x C(dVdT)µs
SHUTDOWN entry delaySHDN↓ (below SHUTF) to FLT↓6.83µs
OVER VOLTAGE PROTECTION INPUT (OVP)
tOVP(dly)OVP Exit delayOVP↓ (20 mV below V(OVPF)) to V(OUT) = 100 mV, TPS26620/21/24/25 Only77µs
OVP Disable delayOVP↑ (20mV above V(OVPR)) to FLT↓ ,   TPS26620/21/24/25 Only4.84µs
CURRENT LIMIT
tCL(dly)Maximum duration in current limitI(ILIM) < I(OUT) < I(FAST-TRIP), V(IN) – V(OUT) < 2.6 V512ms
tFAST-TRIP(dly)Fast-Trip Comparator DelayI(OUT) > I(FAST-TRIP), V(IN) – V(OUT)  = 2 V1.5µs
I(OUT) > I(FAST-TRIP), 4.5 V < V(IN) ≤ 6 V, V(IN) – V(OUT) ≥ 2.6 V1.4µs
I(OUT) > I(FAST-TRIP), 6 V < V(IN) ≤ 57 V, V(IN) – V(OUT) ≥ 2.6 V220ns
REVERSE PROTECTION COMPARATOR
tREV(dly)Reverse Protection Comparator Delay(V(IN) – V(OUT)) ↓ (10 mV overdrive below V(REVTH)) to internal FET turn OFF15µs
(V(IN) – V(OUT)) ↓ (1 V overdrive below V(REVTH)) to internal FET turn OFF3.71
(V(IN) – V(OUT)) ≤ – 2.6 V to internal FET turn OFF0.31
(V(IN) – V(OUT)) ↓ (150 mV overdrive below V(REVTH)) to FLT↓45
tFWD(dly)(V(IN) – V(OUT)) ↑ (100 mV overdrive above V(FWDTH)) to  FLT↑63
THERMAL SHUTDOWN
Retry Delay in TSD512ms
OUTPUT RAMP CONTROL (dVdT)
tdVdTOutput Ramp TimeSHDN ↑ to V(OUT) = 23.9 V, with C(dVdT) = 22 nF11ms
SHDN ↑ to V(OUT) = 23.9 V, with C(dVdT) = open0.664
FAULT FLAG ( FLT)
tPGOODFPGOOD DelayFalling edge875µs
tPGOODRRising edge, C(dVdT) = Open1.4ms
Rising edge, C(dVdT) > 4.7 nF, [C(dVdT) in nF]750 + 573 x C(dVdT)µs