SLVSF24C december   2020  – may 2023 TPS272C45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Recommended Connections for Unused Pins
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SNS Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Programmable Current Limit
        1. 9.3.1.1 Inrush Current Handling
        2. 9.3.1.2 Calculating RILIMx
        3. 9.3.1.3 Configuring ILIMx From an MCU
      2. 9.3.2 Low Power Dissipation
      3. 9.3.3 Protection Mechanisms
        1. 9.3.3.1 Short-Circuit Protection
          1. 9.3.3.1.1 VS During Short-to-Ground
        2. 9.3.3.2 Inductive Load Demagnetization
        3. 9.3.3.3 Thermal Shutdown
        4. 9.3.3.4 Undervoltage Lockout on VS (UVLO)
        5. 9.3.3.5 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        6. 9.3.3.6 Power-Up and Power-Down Behavior
        7. 9.3.3.7 Overvoltage Protection (OVPR)
      4. 9.3.4 Diagnostic Mechanisms
        1. 9.3.4.1 Current Sense
          1. 9.3.4.1.1 RSNS Value
            1. 9.3.4.1.1.1 Current Sense Output Filter
        2. 9.3.4.2 Fault Indication
          1. 9.3.4.2.1 Fault Event Diagrams
        3. 9.3.4.3 Short-to-Supply or Open-Load Detection
          1. 9.3.4.3.1 Detection With Switch Enabled
          2. 9.3.4.3.2 Detection With Switch Disabled
        4. 9.3.4.4 Current Sense Resistor Sharing
    4. 9.4 Device Functional Modes
      1. 9.4.1 Off
      2. 9.4.2 Diagnostic
      3. 9.4.3 Active
      4. 9.4.4 Fault
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 IEC 61000-4-5 Surge
      2. 10.1.2 Inverse Current
      3. 10.1.3 Loss of GND
      4. 10.1.4 Paralleling Channels
      5. 10.1.5 Thermal Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 RILIM Calculation
        2. 10.2.2.2 Diagnostics
          1. 10.2.2.2.1 Selecting the RISNS Value
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1.1 Inrush Current Handling

The TPS272C45 uses a resistor from the following pins to the IC GND to configure the current limit behavior: ILIM1, ILIM2, and ILIMD. The ILIM1 and ILIM2 pin resistors set the current limit thresholds for CH1 and CH2 respectively while ILIMD pin resistor sets a delay time for the device to operate in a higher or lower current limit during device start-up or output turn-on by retry after a fault (thermal) shutdown).

GUID-20211123-SS0I-MVBG-D6HF-RZK1SGLBGRTF-low.svgFigure 9-2 Current Limit Set Functionality

The ILIM1/ILIM2 thresholds and the ILIMD pin resistor controlled timing enable flexible inrush current control behavior. The following table shows the various options available.

Table 9-1 Inrush Current Limit Options
Case NumberILIMD Resistor SettingsInrush Delay Time (ms)Current Limit During Inrush DurationNotes
1Short to GND0At the level set by ILIM1/2 resistorThe device shows constant current limit threshold in each channel at all times set by the ILIM1/2 resistors.

2

Discrete resistor values

(See table below)

Programmable in discrete steps

2- 18

Current limit at 2 times the level set by ILIM1/2 resistorThe current is set higher during the duration of the inrush delay to support high inrush current loads like incandescent lamps. See figure (case 1) showing current limit behavior enabling into a short circuit with ILIM1/2 threshold set at 2.2 A.
340.2 kΩ +/–2%Fixed 30Current limit fixed at 1.5-A threshold for Vds > 16 V, or at the level set by ILIM1/2 resistor if Vds < 16 VAdditional feature to limit the current and power dissipation during initial phase of charging large power supply capacitor loads. The Vds dependence of current limit exists only during the duration set by the ILIMD resistor.

If the ILIMD resistor is not connected (floating) or > 40.2 kΩ, the inrush current limit behavior defaults to Case 3.

Table 9-2 Delay Resistor Values

ILIMD Resistor Value

Delay

3.48 kΩ

2 ms

7.15 kΩ

4 ms

12.1 kΩ

6 ms

17.8 kΩ

10 ms

24.9 kΩ

18 ms

GUID-20211123-SS0I-RTWP-ZJFV-PMTLP4MDH1BD-low.svgFigure 9-3 Inrush Current Control (Case 2) With a Shorted Load
GUID-20211123-SS0I-9JPC-RF8D-5XX4VZFRQBHK-low.svgFigure 9-4 Inrush Current Control (Case 3) With a Shorted Load

For the Case 2, when the ENx pin goes high to turn on one of the channels (or the channel is turned on automatically to retry after a fault shutdwon), the device defaults to twice current limit threshold as determined by RILIM1/RILIM2 or the maximum internal current limit level (whichever is lower). The internal current limit level is defined in the Specifications section of this document. After a TDELAY period that is determined by RILIMD, the current limit changes to the threshold determined by RILIM1/RILIM2. The delay can be set in the range from 0 (the current limit threshold at all times set to that determined by RILIM1/RILIM2) to a maximum of 22 ms in dscrete steps.

Each channel operates independently with current limit thresholds controlled by RILIM1 and RILIM2(so both channels can have separate current limit thresholds). If channel 2 is enabled after channel one, channel 2 has its own separate timing.

The initial inrush current period when the current limit is higher enables two different system advantages when driving loads

  • Enables higher load current to be supported for a period of time of the order of milliseconds to drive high inrush current loads like incandescent bulb loads.
  • Enables fast capacitive load charging. In some situations, it is ideal to charge capacitive loads at a higher current than the DC current to ensure quick supply bring up. This architecture allows a module to quickly charge a capacitive load using the initial higher inrush current limit and then use a lower current limit to reliably protect the module under overload or short circuit conditions.

While in current limiting mode, at any level, the device has a high power dissipation. If the FET temperature exceeds the over-temperature shutdown threshold, the device turns off just the channel that is overloaded. After cooling down, the device either latches off or re-tries, depending on the state of the LATCH pin. If the device is turning off prematurely on start-up, TI recommends to improve the PCB thermal layout, lower the current limit to lower power dissipation, or decrease the inrush current (capacitive loading).