SLVSD74D December 2015 – December 2019 TPS2H160-Q1
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp between drain and source is implemented, namely VDS(clamp).
During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The total energy is dissipated in the high-side switch. Total energy includes the energy of the power supply (E(VS)) and the energy of the load (E(load)). If resistance is in series with inductance, some of the load energy is dissipated on the resistance.
When an inductive load switches off, E(HSS) causes high thermal stressing on the device.. The upper limit of the power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition.
From the perspective of the high-side switch, E(HSS) equals the integration value during the demagnetization period.
When R approximately equals 0, E(HSD) can be given simply as:
Figure 28 is a waveform of the device driving an inductive load, and Figure 29 is waveform with an expanded time scale. Channel 1 is the IN signal, channel 2 is the supply voltage VVS, channel 3 is the output voltage VOUT, channel 4 is the output current IOUT, and channel M is the measured power dissipation E(HSS).
On the waveform, the duration of VOUT from VVS to (VVS – VDS(clamp)) is around 120 µs. The device also optimizes the switching-off slew rate when the clamp is active. This optimization can help the system design by keeping the effects of transient power and EMI to a minimum. As shown in Figure 28 and Figure 29, the controlled slew rate is around 0.5 V/µs.
Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry shown in Figure 30 to protect the device from repetitive power stressing. TVS is used to achieve the fast decay. See Figure 30 for more details.