SLVSGE8A november   2022  – june 2023 TPS35-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Timeout Watchdog Timer
        1. 8.3.2.1 tWD Timer
        2. 8.3.2.2 Watchdog Enable Disable Operation
        3. 8.3.2.3 tSD Watchdog Start Up Delay
        4. 8.3.2.4 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed watchdog Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Timer Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timings
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting the Voltage Threshold
          2. 9.2.1.2.2 Meeting the Watchdog Timeout Period
          3. 9.2.1.2.3 Setting the Reset Delay
          4. 9.2.1.2.4 Setting the Startup Delay and Output Topology
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4 RESET and WDO Output

The TPS35-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated.

The output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer Section 5 section for all available options.

Equation 2 describes the relationship between capacitor value and the time tD. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.

Equation 2. tD (sec) = 4.95 x 106 x CCRST (F)

TPS35-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. Figure 8-13 shows timing behavior of the device with latched output configuration.

GUID-20230113-SS0I-VQQH-MRSQ-HLWHKNKKSH2Q-low.svg Figure 8-13 Output Latch Timing Behavior